device/dram/ddr2: Add a function to normalize tCLK
Also make most significant bit function accessible outside the scope of this file. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
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* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,6 +24,7 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/dram/ddr2.h>
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#include <lib.h>
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#include <string.h>
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/*==============================================================================
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@ -100,14 +102,9 @@ u32 spd_decode_eeprom_size_ddr2(u8 byte1)
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*
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* Returns the index fof MSB set.
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*/
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static u8 spd_get_msbs(u8 c)
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u8 spd_get_msbs(u8 c)
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{
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int i;
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for (i = 7; i >= 0; i--)
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if (c & (1 << i))
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return i;
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return 0;
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return log2(c);
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}
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/**
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@ -629,3 +626,25 @@ void dram_print_spd_ddr2(const struct dimm_attr_st *dimm)
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print_us(" tPLL : ", dimm->tPLL);
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print_us(" tRR : ", dimm->tRR);
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}
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void normalize_tck(u32 *tclk)
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{
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if (*tclk <= TCK_800MHZ) {
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*tclk = TCK_800MHZ;
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} else if (*tclk <= TCK_666MHZ) {
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*tclk = TCK_666MHZ;
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} else if (*tclk <= TCK_533MHZ) {
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*tclk = TCK_533MHZ;
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} else if (*tclk <= TCK_400MHZ) {
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*tclk = TCK_400MHZ;
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} else if (*tclk <= TCK_333MHZ) {
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*tclk = TCK_333MHZ;
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} else if (*tclk <= TCK_266MHZ) {
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*tclk = TCK_266MHZ;
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} else if (*tclk <= TCK_200MHZ) {
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*tclk = TCK_200MHZ;
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} else {
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*tclk = 0;
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printk(BIOS_ERR, "Too slow common tCLK found\n");
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}
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}
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@ -213,6 +213,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0);
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u32 spd_decode_eeprom_size_ddr2(u8 byte1);
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int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);
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void dram_print_spd_ddr2(const struct dimm_attr_st *dimm);
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void normalize_tck(u32 *tclk);
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u8 spd_get_msbs(u8 c);
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#endif /* DEVICE_DRAM_DDR2L_H */
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