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device/dram/ddr2: Add a function to normalize tCLK 

Also make most significant bit function accessible outside the scope
of this file.

Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2017-03-01 20:10:55 +01:00 committed by Martin Roth
parent 5744369025
commit 3397aa1fd4
2 changed files with 28 additions and 8 deletions
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33
src/device/dram/ddr2.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org> * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
* *
* This program is free software: you can redistribute it and/or modify * This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -23,6 +24,7 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/dram/ddr2.h> #include <device/dram/ddr2.h>
#include <lib.h>
#include <string.h> #include <string.h>
/*============================================================================== /*==============================================================================
@ -100,14 +102,9 @@ u32 spd_decode_eeprom_size_ddr2(u8 byte1)
* *
* Returns the index fof MSB set. * Returns the index fof MSB set.
*/ */
static u8 spd_get_msbs(u8 c) u8 spd_get_msbs(u8 c)
{ {
int i; return log2(c);
for (i = 7; i >= 0; i--)
if (c & (1 << i))
return i;
return 0;
} }
/** /**
@ -629,3 +626,25 @@ void dram_print_spd_ddr2(const struct dimm_attr_st *dimm)
print_us(" tPLL : ", dimm->tPLL); print_us(" tPLL : ", dimm->tPLL);
print_us(" tRR : ", dimm->tRR); print_us(" tRR : ", dimm->tRR);
} }
void normalize_tck(u32 *tclk)
{
if (*tclk <= TCK_800MHZ) {
*tclk = TCK_800MHZ;
} else if (*tclk <= TCK_666MHZ) {
*tclk = TCK_666MHZ;
} else if (*tclk <= TCK_533MHZ) {
*tclk = TCK_533MHZ;
} else if (*tclk <= TCK_400MHZ) {
*tclk = TCK_400MHZ;
} else if (*tclk <= TCK_333MHZ) {
*tclk = TCK_333MHZ;
} else if (*tclk <= TCK_266MHZ) {
*tclk = TCK_266MHZ;
} else if (*tclk <= TCK_200MHZ) {
*tclk = TCK_200MHZ;
} else {
*tclk = 0;
printk(BIOS_ERR, "Too slow common tCLK found\n");
}
}

3
src/include/device/dram/ddr2.h
View File

@ -213,6 +213,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0);
u32 spd_decode_eeprom_size_ddr2(u8 byte1); u32 spd_decode_eeprom_size_ddr2(u8 byte1);
int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]); int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);
void dram_print_spd_ddr2(const struct dimm_attr_st *dimm); void dram_print_spd_ddr2(const struct dimm_attr_st *dimm);
void normalize_tck(u32 *tclk);
u8 spd_get_msbs(u8 c);
#endif /* DEVICE_DRAM_DDR2L_H */ #endif /* DEVICE_DRAM_DDR2L_H */