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urara: Configure UART line control to 8N1 

8bit, 1 stop bit, no parity

BUG=chrome-os-partner:31438
TEST=built urara bootblock and ran it on the Pistachio FPGA, observed
      expected console output.
BRANCH=none

Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e
Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226551
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9185
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Ionela Voinescu 2014-10-30 14:49:53 +00:00 committed by Stefan Reinauer
parent b92e54333f
commit 33c10f8c32
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/urara/Kconfig
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@ -46,4 +46,8 @@ config DRAM_SIZE_MB
int
default 256
config TTYS0_LCS
int
default 3
endif