This patch uses auto.c from Uwe's tyan s1846 for both boards, with some
minor changes, to bring them up to par. It also should remove (but might just clean out) the irq_tables.c from both boards, because they were just copied from Via Epia to begin with, and weren't usable. As far as I can tell, these are the only changes needed to the targets for now, aside from fixups to reset.c when the time comes. Both have been build tested, but not checked on hardware since I don't have it. I have left Uwe as the copyright holder since the only changes I've made are trivial. Signed-off-by: Corey Osgood <corey_osgood@verizon.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Corey Osgood
Uwe Hermann
parent
a440f7fd8c
commit
33d1af37ae
|
|
@ -1,3 +1,23 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
|
|
@ -17,8 +37,6 @@
|
|||
|
||||
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
|
||||
|
||||
/*
|
||||
*/
|
||||
void udelay(int usecs)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -29,82 +47,41 @@ void udelay(int usecs)
|
|||
#include "debug.c"
|
||||
#include "lib/delay.c"
|
||||
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
static void enable_mainboard_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
/* dev 0 for southbridge */
|
||||
|
||||
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
|
||||
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Southbridge not found!!!\n");
|
||||
}
|
||||
pci_write_config8(dev, 0x50, 7);
|
||||
pci_write_config8(dev, 0x51, 0xff);
|
||||
#if 0
|
||||
// This early setup switches IDE into compatibility mode before PCI gets
|
||||
// // a chance to assign I/Os
|
||||
// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
|
||||
// // movb $0x09, %dl
|
||||
// movb $0x00, %dl
|
||||
// PCI_WRITE_CONFIG_BYTE
|
||||
//
|
||||
#endif
|
||||
/* we do this here as in V2, we can not yet do raw operations
|
||||
* to pci!
|
||||
*/
|
||||
dev += 0x100; /* ICKY */
|
||||
|
||||
pci_write_config8(dev, 0x42, 0);
|
||||
}
|
||||
|
||||
static void enable_shadow_ram(void)
|
||||
{
|
||||
device_t dev = 0; /* no need to look up 0:0.0 */
|
||||
unsigned char shadowreg;
|
||||
/* dev 0 for southbridge */
|
||||
shadowreg = pci_read_config8(dev, 0x63);
|
||||
uint8_t shadowreg;
|
||||
/* dev 0 for northbridge */
|
||||
shadowreg = pci_read_config8(0, 0x59);
|
||||
/* 0xf0000-0xfffff */
|
||||
shadowreg |= 0x30;
|
||||
pci_write_config8(dev, 0x63, shadowreg);
|
||||
pci_write_config8(0, 0x59, shadowreg);
|
||||
}
|
||||
|
||||
/* TODO: fix raminit.c to use smbus_read_byte */
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
unsigned char c;
|
||||
uint8_t c;
|
||||
c = smbus_read_byte(device, address);
|
||||
return c;
|
||||
}
|
||||
|
||||
|
||||
#include "northbridge/intel/i440bx/raminit.c"
|
||||
#include "northbridge/intel/i440bx/debug.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.channel0 = {
|
||||
(0xa << 3) | 0,
|
||||
(0xa << 3) | 1,
|
||||
(0xa << 3) | 2, (0xa << 3) | 3,
|
||||
},
|
||||
(0xa << 3) | 0,
|
||||
(0xa << 3) | 1,
|
||||
(0xa << 3) | 2,
|
||||
(0xa << 3) | 3,
|
||||
},
|
||||
}
|
||||
};
|
||||
unsigned long x;
|
||||
|
||||
if (bist == 0) {
|
||||
early_mtrr_init();
|
||||
|
|
@ -116,39 +93,27 @@ static void main(unsigned long bist)
|
|||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
enable_smbus();
|
||||
dump_spd_registers(&cpu[0]);
|
||||
|
||||
#if 0
|
||||
enable_shadow_ram();
|
||||
/*
|
||||
memreset_setup();
|
||||
this is way more generic than we need.
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
*/
|
||||
sdram_set_registers((const struct mem_controller *) 0);
|
||||
sdram_set_spd_registers((const struct mem_controller *) 0);
|
||||
sdram_enable(0, (const struct mem_controller *) 0);
|
||||
#endif
|
||||
|
||||
/* Check all of memory */
|
||||
#if 0
|
||||
ram_check(0x00000000, msr.lo);
|
||||
#endif
|
||||
#if 0
|
||||
static const struct {
|
||||
unsigned long lo, hi;
|
||||
} check_addrs[] = {
|
||||
/* Check 16MB of memory @ 0*/
|
||||
{ 0x00000000, 0x01000000 },
|
||||
#if TOTAL_CPUS > 1
|
||||
/* Check 16MB of memory @ 2GB */
|
||||
{ 0x80000000, 0x81000000 },
|
||||
#endif
|
||||
};
|
||||
int i;
|
||||
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
|
||||
ram_check(check_addrs[i].lo, check_addrs[i].hi);
|
||||
}
|
||||
#endif
|
||||
|
||||
enable_smbus();
|
||||
|
||||
dump_spd_registers(&memctrl[0]);
|
||||
|
||||
sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
|
||||
|
||||
/* Check whether RAM is working.
|
||||
*
|
||||
* Do _not_ check the area from 640 KB - 1 MB, as that's not really
|
||||
* RAM, but rather reserved for various other things:
|
||||
*
|
||||
* - 640 KB - 768 KB: Video Buffer Area
|
||||
* - 768 KB - 896 KB: Expansion Area
|
||||
* - 896 KB - 960 KB: Extended System BIOS Area
|
||||
* - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area
|
||||
*
|
||||
* Trying to check these areas will fail.
|
||||
*/
|
||||
/* TODO: This is currently hardcoded to check 64 MB. */
|
||||
ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */
|
||||
ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*5, /* there can be total 5 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0x88, /* Where the interrupt router lies (dev) */
|
||||
0x1c20, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1106, /* Vendor */
|
||||
0x8231, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* 8231 ethernet */
|
||||
{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
|
||||
/* 8231 internal */
|
||||
{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
|
||||
/* PCI slot */
|
||||
{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
|
||||
{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
|
||||
{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
|
||||
}
|
||||
};
|
||||
|
|
@ -17,8 +17,6 @@
|
|||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
|
||||
|
||||
/*
|
||||
*/
|
||||
void udelay(int usecs)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -29,84 +27,41 @@ void udelay(int usecs)
|
|||
#include "debug.c"
|
||||
#include "lib/delay.c"
|
||||
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
static void enable_mainboard_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
/* dev 0 for southbridge */
|
||||
|
||||
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
|
||||
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Southbridge not found!!!\n");
|
||||
}
|
||||
pci_write_config8(dev, 0x50, 7);
|
||||
pci_write_config8(dev, 0x51, 0xff);
|
||||
#if 0
|
||||
// This early setup switches IDE into compatibility mode before PCI gets
|
||||
// // a chance to assign I/Os
|
||||
// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
|
||||
// // movb $0x09, %dl
|
||||
// movb $0x00, %dl
|
||||
// PCI_WRITE_CONFIG_BYTE
|
||||
//
|
||||
#endif
|
||||
/* we do this here as in V2, we can not yet do raw operations
|
||||
* to pci!
|
||||
*/
|
||||
dev += 0x100; /* ICKY */
|
||||
|
||||
pci_write_config8(dev, 0x42, 0);
|
||||
}
|
||||
|
||||
static void enable_shadow_ram(void)
|
||||
{
|
||||
device_t dev = 0; /* no need to look up 0:0.0 */
|
||||
unsigned char shadowreg;
|
||||
/* dev 0 for southbridge */
|
||||
shadowreg = pci_read_config8(dev, 0x63);
|
||||
uint8_t shadowreg;
|
||||
/* dev 0 for northbridge */
|
||||
shadowreg = pci_read_config8(0, 0x59);
|
||||
/* 0xf0000-0xfffff */
|
||||
shadowreg |= 0x30;
|
||||
pci_write_config8(dev, 0x63, shadowreg);
|
||||
pci_write_config8(0, 0x59, shadowreg);
|
||||
}
|
||||
|
||||
/* TODO: fix raminit.c to use smbus_read_byte */
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
int c;
|
||||
uint8_t c;
|
||||
c = smbus_read_byte(device, address);
|
||||
return c;
|
||||
}
|
||||
|
||||
|
||||
#include "northbridge/intel/i440bx/raminit.c"
|
||||
#include "northbridge/intel/i440bx/debug.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.channel0 = {
|
||||
(0xa << 3) | 0,
|
||||
(0xa << 3) | 1,
|
||||
(0xa << 3) | 2,
|
||||
(0xa << 3) | 3,
|
||||
},
|
||||
(0xa << 3) | 0,
|
||||
(0xa << 3) | 1,
|
||||
(0xa << 3) | 2,
|
||||
(0xa << 3) | 3,
|
||||
},
|
||||
}
|
||||
};
|
||||
unsigned long x;
|
||||
int result;
|
||||
|
||||
if (bist == 0) {
|
||||
early_mtrr_init();
|
||||
|
|
@ -117,46 +72,28 @@ static void main(unsigned long bist)
|
|||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
enable_smbus();
|
||||
/*
|
||||
result = spd_read_byte(cpu[0].channel0[0],0x03);
|
||||
print_debug("Result: ");
|
||||
print_debug_hex16(result);
|
||||
print_debug("\r\n");
|
||||
*/
|
||||
dump_spd_registers(&cpu[0]);
|
||||
|
||||
#if 0
|
||||
enable_shadow_ram();
|
||||
/*
|
||||
memreset_setup();
|
||||
this is way more generic than we need.
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
*/
|
||||
sdram_set_registers((const struct mem_controller *) 0);
|
||||
sdram_set_spd_registers((const struct mem_controller *) 0);
|
||||
sdram_enable(0, (const struct mem_controller *) 0);
|
||||
#endif
|
||||
|
||||
/* Check all of memory */
|
||||
#if 0
|
||||
ram_check(0x00000000, msr.lo);
|
||||
#endif
|
||||
#if 0
|
||||
static const struct {
|
||||
unsigned long lo, hi;
|
||||
} check_addrs[] = {
|
||||
/* Check 16MB of memory @ 0*/
|
||||
{ 0x00000000, 0x01000000 },
|
||||
#if TOTAL_CPUS > 1
|
||||
/* Check 16MB of memory @ 2GB */
|
||||
{ 0x80000000, 0x81000000 },
|
||||
#endif
|
||||
};
|
||||
int i;
|
||||
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
|
||||
ram_check(check_addrs[i].lo, check_addrs[i].hi);
|
||||
}
|
||||
#endif
|
||||
|
||||
enable_smbus();
|
||||
|
||||
dump_spd_registers(&memctrl[0]);
|
||||
|
||||
sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
|
||||
|
||||
/* Check whether RAM is working.
|
||||
*
|
||||
* Do _not_ check the area from 640 KB - 1 MB, as that's not really
|
||||
* RAM, but rather reserved for various other things:
|
||||
*
|
||||
* - 640 KB - 768 KB: Video Buffer Area
|
||||
* - 768 KB - 896 KB: Expansion Area
|
||||
* - 896 KB - 960 KB: Extended System BIOS Area
|
||||
* - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area
|
||||
*
|
||||
* Trying to check these areas will fail.
|
||||
*/
|
||||
/* TODO: This is currently hardcoded to check 64 MB. */
|
||||
ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */
|
||||
ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*5, /* there can be total 5 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0x88, /* Where the interrupt router lies (dev) */
|
||||
0x1c20, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1106, /* Vendor */
|
||||
0x8231, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* 8231 ethernet */
|
||||
{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
|
||||
/* 8231 internal */
|
||||
{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
|
||||
/* PCI slot */
|
||||
{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
|
||||
{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
|
||||
{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
|
||||
}
|
||||
};
|
||||
Loading…
Reference in New Issue