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amd/stoneyridge: Remove unused registers from ASL 

Remove AcpiMmio and PCI config registers that are not used.

TEST=build Grunt
BUG=b:77602074

Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2018-10-01 14:51:50 -06:00 committed by Martin Roth
parent 0425b0a4bb
commit 33d4f73eef
1 changed files with 0 additions and 71 deletions
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71
src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
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@ -309,12 +309,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
, 4, , 4,
U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */ U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */
SDSR, 1, /* SD 24 Shadow Reg Request Status Register */ SDSR, 1, /* SD 24 Shadow Reg Request Status Register */
offset (0x1e88),
SRSA, 32, /* Shadow Reg SRAM Addr */
SRSD, 32, /* Shadow Reg SRAM DATA */
offset (0x1e94),
SRDY, 1, /* S0i3 bios ready */
offset (0x1ea0), offset (0x1ea0),
PG1A, 1, PG1A, 1,
@ -341,40 +335,6 @@ Field(FCFG, DwordAcc, NoLock, Preserve)
Offset(0x00080054), Offset(0x00080054),
U_PS, 2, U_PS, 2,
/* SATA */
Offset(0x00088010),
ST10, 32,
ST14, 32,
ST18, 32,
ST1C, 32,
ST20, 32,
ST24, 32,
Offset(0x0008802c),
ST2C, 32,
Offset(0x00088040),
ST40, 1,
Offset(0x00088044),
ST44, 1,
Offset(0x0008804c),
, 2,
DDIC, 1, /* DisableDynamicInterfaceClockPowerSaving */
Offset(0x00088064),
S_PS, 2,
Offset(0x00088084),
, 1,
ST84, 1,
, 28,
DSDN, 1, /* DShutDowN */
Offset(0x0008808c),
ST8C, 8,
/* EHCI */ /* EHCI */
Offset(0x00090004), Offset(0x00090004),
, 1, , 1,
@ -392,40 +352,9 @@ Field(FCFG, DwordAcc, NoLock, Preserve)
E_PS, 2, E_PS, 2,
/* LPC Bridge */ /* LPC Bridge */
Offset(0x000a3078),
, 2,
LDQ0, 1,
Offset(0x000a30cb), Offset(0x000a30cb),
, 7, , 7,
AUSS, 1, /* AutoSizeStart */ AUSS, 1, /* AutoSizeStart */
/* SD */
Offset(0x000a7004),
, 1,
SDME, 1,
Offset(0x000a7010),
SDBA, 32,
Offset(0x000a702c),
SD2C, 32,
Offset(0x000a7094),
D_PS, 2,
, 6,
SDPE, 1,
, 6,
PMES, 1,
Offset(0x000a70b3), /* Version 2.0 = 0x1, Version 3.0 = 0x2 */
SDB3, 8,
Offset(0x000a70b4), /* Set Enable */
, 8,
SETE, 1,
Offset(0x000a70d0),
, 17,
FC18, 1, /* Force 1.8v */
} }
/* /*