samus: Tweaks from bringup
- GPIO29 is no longer connected so we don't need the SMI workaround on the entry to sleep states. - Disable touchscreen wake source until the kernel driver is working so it does not wake immediately. - Update a few GPIOs and disable the codec for now as it is leaking into the 1.8V DDR rail. Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -99,6 +99,7 @@ Scope (\_SB)
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}
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}
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})
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})
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#if 0 // Disabled until kernel driver is working
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Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
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Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
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Method (_DSW, 3, NotSerialized)
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Method (_DSW, 3, NotSerialized)
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@ -110,5 +111,6 @@ Scope (\_SB)
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\_SB.PCI0.LPCB.GWAK (Local0)
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\_SB.PCI0.LPCB.GWAK (Local0)
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}
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}
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}
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}
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#endif
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}
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}
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}
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}
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@ -52,7 +52,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
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LP_GPIO_OUT_HIGH, /* 26: NFC_EN */
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LP_GPIO_OUT_HIGH, /* 26: NFC_EN */
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LP_GPIO_UNUSED, /* 27: UNUSED */
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LP_GPIO_UNUSED, /* 27: UNUSED */
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LP_GPIO_IRQ_EDGE, /* 29: NFC_INT (GPIO IRQ) */
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LP_GPIO_IRQ_EDGE, /* 29: NFC_INT (GPIO IRQ) */
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LP_GPIO_NATIVE, /* 29: NATIVE: WLAN_OFF_L */
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LP_GPIO_UNUSED, /* 29: UNUSED */
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LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
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LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
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LP_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
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LP_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
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LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
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LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
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@ -67,12 +67,12 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
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LP_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
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LP_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
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LP_GPIO_IRQ_EDGE, /* 42: CODEC_INT_L (GPIO IRQ) */
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LP_GPIO_IRQ_EDGE, /* 42: CODEC_INT_L (GPIO IRQ) */
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LP_GPIO_IRQ_EDGE, /* 43: ACCEL_INT (GPIO IRQ) */
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LP_GPIO_IRQ_EDGE, /* 43: ACCEL_INT (GPIO IRQ) */
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LP_GPIO_OUT_HIGH, /* 44: CODEC_LDOENA */
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LP_GPIO_OUT_LOW, /* 44: CODEC_LDOENA (DISABLED FOR BRINGUP) */
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LP_GPIO_OUT_HIGH, /* 45: PP1800_CODEC_EN */
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LP_GPIO_OUT_LOW, /* 45: PP1800_CODEC_EN (DISABLED FOR BRINGUP) */
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LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
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LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
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LP_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */
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LP_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */
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LP_GPIO_UNUSED, /* 48: UNUSED */
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LP_GPIO_UNUSED, /* 48: UNUSED */
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LP_GPIO_OUT_HIGH, /* 49: HDMI_CEC */
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LP_GPIO_INPUT, /* 49: HDMI_CEC */
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LP_GPIO_UNUSED, /* 50: UNUSED */
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LP_GPIO_UNUSED, /* 50: UNUSED */
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LP_GPIO_UNUSED, /* 51: UNUSED */
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LP_GPIO_UNUSED, /* 51: UNUSED */
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LP_GPIO_INPUT, /* 52: SIM_DET */
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LP_GPIO_INPUT, /* 52: SIM_DET */
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@ -80,15 +80,15 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
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LP_GPIO_UNUSED, /* 54: UNUSED */
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LP_GPIO_UNUSED, /* 54: UNUSED */
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LP_GPIO_UNUSED, /* 55: UNUSED */
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LP_GPIO_UNUSED, /* 55: UNUSED */
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LP_GPIO_UNUSED, /* 56: UNUSED */
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LP_GPIO_UNUSED, /* 56: UNUSED */
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LP_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */
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LP_GPIO_OUT_LOW, /* 57: CODEC_RESET_L (DISABLED FOR BRINGUP) */
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LP_GPIO_UNUSED, /* 58: UNUSED */
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LP_GPIO_UNUSED, /* 58: UNUSED */
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LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
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LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
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LP_GPIO_UNUSED, /* 60: UNUSED */
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LP_GPIO_UNUSED, /* 60: UNUSED */
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LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
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LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
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LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
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LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
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LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
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LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
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LP_GPIO_OUT_HIGH, /* 64: NFS_FW_UPDATE */
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LP_GPIO_OUT_HIGH, /* 64: NFC_FW_UPDATE */
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LP_GPIO_OUT_HIGH, /* 65: MINIDP_PWR_FLT_L */
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LP_GPIO_INPUT, /* 65: MINIDP_PWR_FLT_L */
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LP_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */
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LP_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */
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LP_GPIO_INPUT, /* 67: RAM_ID0 */
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LP_GPIO_INPUT, /* 67: RAM_ID0 */
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LP_GPIO_INPUT, /* 68: RAM_ID1 */
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LP_GPIO_INPUT, /* 68: RAM_ID1 */
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@ -92,26 +92,6 @@ void mainboard_smi_gpi(u32 gpi_sts)
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}
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}
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}
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}
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static void mainboard_wlan_off(void)
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{
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u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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u32 gpio_conf;
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/* Make sure pin is owned by GPIO subsystem and not ACPI */
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gpio_conf = inl(gpio_base + GPIO_OWNER(0));
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gpio_conf |= GPIO_OWNER_GPIO << 29;
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outl(gpio_conf, gpio_base + GPIO_OWNER(0));
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/* Set GPIO29 config to only be reset on RSMRST */
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gpio_conf = inl(gpio_base + GPIO_RESET(0));
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gpio_conf |= GPIO_RESET_RSMRST << 29;
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outl(gpio_conf, gpio_base + GPIO_RESET(0));
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/* Set WLAN_OFF_L (GPIO29) as Output GPIO driven high */
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gpio_conf = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH;
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outl(gpio_conf, gpio_base + GPIO_CONFIG0(29));
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}
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void mainboard_smi_sleep(u8 slp_typ)
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void mainboard_smi_sleep(u8 slp_typ)
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{
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{
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/* Disable USB charging if required */
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/* Disable USB charging if required */
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@ -150,9 +130,6 @@ void mainboard_smi_sleep(u8 slp_typ)
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break;
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break;
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}
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}
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/* Set WLAN_OFF GPIO state */
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mainboard_wlan_off();
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/* Disable SCI and SMI events */
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/* Disable SCI and SMI events */
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google_chromeec_set_smi_mask(0);
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google_chromeec_set_smi_mask(0);
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google_chromeec_set_sci_mask(0);
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google_chromeec_set_sci_mask(0);
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