soc/intel/elkhartlake: Update FSP-M UPD related configs

Upload the FSP-M UPD configs. This CL also updated the chip.h and
devicetree.cb with the relevant variables and configs.
This CL also updated the GPIO related settings (PMC & SD card) in
devicetree.cb.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb

@@ -4,6 +4,48 @@ chip soc/intel/elkhartlake
 		device lapic 0 on end
 	end
 
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Enabled"
+	register "SmbusEnable" = "1"
+	register "Heci2Enable" = "1"
+
+	# Skip the CPU repalcement check
+	register "SkipCpuReplacementCheck" = "1"
+
+	# Enable All Root Ports (1-7)
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpEnable[6]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "0x00"
+	register "PcieClkSrcUsage[1]" = "0x06"
+	register "PcieClkSrcUsage[2]" = "0x04"
+	register "PcieClkSrcUsage[3]" = "0xFF"
+	register "PcieClkSrcUsage[4]" = "0xFF"
+	register "PcieClkSrcUsage[5]" = "0xFF"
+
+	register "PcieClkSrcClkReq[0]" = "0x0"
+	register "PcieClkSrcClkReq[1]" = "0x1"
+	register "PcieClkSrcClkReq[2]" = "0x2"
+	register "PcieClkSrcClkReq[3]" = "0x3"
+	register "PcieClkSrcClkReq[4]" = "0x4"
+	register "PcieClkSrcClkReq[5]" = "0x5"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device

src/soc/intel/elkhartlake/chip.h

@@ -19,9 +19,10 @@
 #include <soc/usb.h>
 #include <stdint.h>
 
-#define MAX_HD_AUDIO_DMIC_LINKS 2
+#define MAX_HD_AUDIO_SDI_LINKS	2
-#define MAX_HD_AUDIO_SNDW_LINKS 4
+#define MAX_HD_AUDIO_DMIC_LINKS	2
-#define MAX_HD_AUDIO_SSP_LINKS  6
+#define MAX_HD_AUDIO_SNDW_LINKS	4
+#define MAX_HD_AUDIO_SSP_LINKS	6
 
 struct soc_intel_elkhartlake_config {
 
@@ -63,16 +64,15 @@ struct soc_intel_elkhartlake_config {
 	/* TCC activation offset */
 	uint32_t tcc_offset;
 
-	/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
+	/* System Agent dynamic frequency support.
-	 * When enabled memory will be training at two different frequencies.
+	 * When enabled memory will be trained at different frequencies.
-	 * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
+	 * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2
-	 * 4:FixedPoint3, 5:Enabled */
+	 * (high), 4:Enabled */
 	enum {
 		SaGv_Disabled,
 		SaGv_FixedPoint0,
 		SaGv_FixedPoint1,
 		SaGv_FixedPoint2,
-		SaGv_FixedPoint3,
 		SaGv_Enabled,
 	} SaGv;
 
@@ -96,12 +96,10 @@ struct soc_intel_elkhartlake_config {
 	/* Audio related */
 	uint8_t PchHdaDspEnable;
 	uint8_t PchHdaAudioLinkHdaEnable;
+	uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS];
 	uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
 	uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
 	uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
-	uint8_t PchHdaIDispLinkTmode;
-	uint8_t PchHdaIDispLinkFrequency;
-	uint8_t PchHdaIDispCodecDisconnect;
 
 	/* PCIe Root Ports */
 	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
@@ -128,6 +126,10 @@ struct soc_intel_elkhartlake_config {
 	/* Enable if SD Card Power Enable Signal is Active High */
 	uint8_t SdCardPowerEnableActiveHigh;
 
+	/* Gfx related */
+	uint8_t Heci2Enable;
+	uint8_t Heci3Enable;
+
 	/* Gfx related */
 	uint8_t SkipExtGfxScan;
 
@@ -198,10 +200,6 @@ struct soc_intel_elkhartlake_config {
 	/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
 	bool CnviBtAudioOffload;
 
-	/* Tcss */
-	uint8_t TcssXhciEn;
-	uint8_t TcssXdciEn;
-
 	/*
 	 * Override GPIO PM configuration:
 	 * 0: Use FSP default GPIO PM program,

src/soc/intel/elkhartlake/romstage/fsp_params.c

@@ -1,16 +1,138 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <assert.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <fsp/util.h>
+#include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <string.h>
 
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_elkhartlake_config *config)
 {
-	/* TODO: Update with UPD details as FSP matures */
+	unsigned int i;
+	const struct device *dev;
+	uint32_t mask = 0;
+
+	/*
+	 * If IGD is enabled, set IGD stolen size to 60MB.
+	 * Otherwise, skip IGD init in FSP.
+	 */
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev);
+	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
+
+	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+	m_cfg->SaGv = config->SaGv;
+	m_cfg->RMT = config->RMT;
+
+	/* PCIe root port configuration */
+	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+		if (config->PcieRpEnable[i])
+			mask |= (1 << i);
+	}
+
+	m_cfg->PcieRpEnableMask = mask;
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >=
+			ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!");
+	memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
+			sizeof(config->PcieClkSrcUsage));
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >=
+			ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!");
+	memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+			sizeof(config->PcieClkSrcClkReq));
+
+	m_cfg->PrmrrSize = config->PrmrrSize;
+
+	/* Disable BIOS Guard */
+	m_cfg->BiosGuard = 0;
+
+	/* Set CPU Ratio */
+	m_cfg->CpuRatio = 0;
+
+	/* Set debug interface flags */
+	m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
+		DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
+
+	/* TraceHub configuration */
+	dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
+	if (is_dev_enabled(dev) && config->TraceHubMode) {
+		m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
+		m_cfg->PchTraceHubMode = config->TraceHubMode;
+		m_cfg->CpuTraceHubMode = config->TraceHubMode;
+	}
+
+	/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
+	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+
+	/* PCH Master Gating Control */
+	m_cfg->PchMasterClockGating = 1;
+	m_cfg->PchMasterPowerGating = 1;
+
+	/* Enable SMBus controller based on config */
+	m_cfg->SmbusEnable = config->SmbusEnable;
+
+	/* Set debug probe type */
+	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT;
+
+	/* DMAR related config */
+	m_cfg->VtdDisable = 0;
+	m_cfg->X2ApicOptOut = 0x1;
+	if (m_cfg->InternalGfx) {
+		m_cfg->VtdIgdEnable = 0x1;
+		m_cfg->DisableTeIgd = 0x1;
+		m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
+	}
+	m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
+
+	/* DllBwEn0/1/2/3, per frequency */
+	m_cfg->DllBwEn0 = 0;
+	m_cfg->DllBwEn1 = 0;
+	m_cfg->DllBwEn2 = 0;
+	m_cfg->DllBwEn3 = 0;
+
+	/* Disable and Lock Watch Dog Register */
+	m_cfg->WdtDisableAndLock = 0x1;
+
+	m_cfg->HeciCommunication2 = config->Heci2Enable;
+	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+
+	/* Audio */
+	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
+	m_cfg->PchHdaEnable = is_dev_enabled(dev);
+	m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
+	m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PchHdaSdiEnable) >=
+			ARRAY_SIZE(config->PchHdaSdiEnable), "copy buffer overflow!");
+	memcpy(m_cfg->PchHdaSdiEnable, config->PchHdaSdiEnable,
+		sizeof(config->PchHdaSdiEnable));
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >=
+			ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!");
+	memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
+		sizeof(config->PchHdaAudioLinkDmicEnable));
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >=
+			ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!");
+	memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
+		sizeof(config->PchHdaAudioLinkSspEnable));
+
+	_Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >=
+			ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!");
+	memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
+		sizeof(config->PchHdaAudioLinkSndwEnable));
+
+	/* Skip the CPU replacement check */
+	m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck;
+
+	/* Processor Early Power On Configuration FCLK setting */
+	m_cfg->FClkFrequency = 0x1;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
@@ -20,13 +142,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	soc_memory_init_params(m_cfg, config);
 
-	/* Set debug probe type */
-	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT;
-
 	mainboard_memory_init_params(mupd);
 }
 
 __weak void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	/* TODO: Update later together with UPD updates */
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }