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binaryPI: Use pcidev_on_root() 

We have constant CONFIG_CBB==0, replace ill dev_find_slot()
with safe pcidev_on_root();

Change-Id: If536adf11aacef8faa3455692285552f97531df9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2018-05-22 01:15:22 +03:00
parent 153ff207ad
commit 33ff44c37c
8 changed files with 27 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/amd/pi/00630F01/dimmSpd.c
View File

@ -27,7 +27,7 @@
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
{
int spdAddress;
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
DEVTREE_CONST struct northbridge_amd_pi_00630F01_config *config = dev->chip_info;
if ((dev == 0) || (config == 0))

12
src/northbridge/amd/pi/00630F01/northbridge.c
View File

@ -108,7 +108,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
return pcidev_on_root(CONFIG_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@ -859,7 +859,7 @@ static void cpu_bus_scan(struct device *dev)
printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics));
dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
dev_mc = pcidev_on_root(CONFIG_CDB, 0);
if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
die("");
@ -888,7 +888,7 @@ static void cpu_bus_scan(struct device *dev)
pbus = dev_mc->bus;
/* Find the cpu's pci device */
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
cdb_dev = pcidev_on_root(devn, 0);
if (!cdb_dev) {
/* If I am probing things in a weird order
* ensure all of the cpu's pci devices are found.
@ -898,7 +898,7 @@ static void cpu_bus_scan(struct device *dev)
cdb_dev = pci_probe_dev(NULL, pbus,
PCI_DEVFN(devn, fn));
}
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
cdb_dev = pcidev_on_root(devn, 0);
} else {
/* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned
@ -910,11 +910,11 @@ static void cpu_bus_scan(struct device *dev)
family = (family >> 20) & 0xFF;
if (family == 1) { //f10
u32 dword;
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 3));
cdb_dev = pcidev_on_root(devn, 3);
dword = pci_read_config32(cdb_dev, 0xe8);
siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
} else if (family == 6) {//f15
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5));
cdb_dev = pcidev_on_root(devn, 5);
if (cdb_dev && cdb_dev->enabled) {
siblings = pci_read_config32(cdb_dev, 0x84);
siblings &= 0xFF;

2
src/northbridge/amd/pi/00660F01/dimmSpd.c
View File

@ -26,7 +26,7 @@
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
{
int spdAddress;
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
if ((dev == 0) || (config == 0))

14
src/northbridge/amd/pi/00660F01/northbridge.c
View File

@ -106,7 +106,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
return pcidev_on_root(CONFIG_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@ -556,12 +556,12 @@ static void fam15_finalize(void *chip_info)
{
struct device *dev;
u32 value;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xF8, 0);
pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
/* disable No Snoop */
dev = dev_find_slot(0, PCI_DEVFN(1, 1));
dev = pcidev_on_root(1, 1);
value = pci_read_config32(dev, 0x60);
value &= ~(1 << 11);
pci_write_config32(dev, 0x60, value);
@ -848,7 +848,7 @@ static void cpu_bus_scan(struct device *dev)
ioapic_count = (int)options->CfgPlatNumIoApics;
ASSERT(ioapic_count > 0);
dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
dev_mc = pcidev_on_root(CONFIG_CDB, 0);
if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
die("");
@ -877,7 +877,7 @@ static void cpu_bus_scan(struct device *dev)
pbus = dev_mc->bus;
/* Find the cpu's pci device */
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
cdb_dev = pcidev_on_root(devn, 0);
if (!cdb_dev) {
/* If I am probing things in a weird order
* ensure all of the cpu's pci devices are found.
@ -887,7 +887,7 @@ static void cpu_bus_scan(struct device *dev)
cdb_dev = pci_probe_dev(NULL, pbus,
PCI_DEVFN(devn, fn));
}
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
cdb_dev = pcidev_on_root(devn, 0);
} else {
/* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned
@ -899,7 +899,7 @@ static void cpu_bus_scan(struct device *dev)
family = (family >> 20) & 0xFF;
if (family == 6 || family == 7) {
/* f15 and f16 */
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5));
cdb_dev = pcidev_on_root(devn, 5);
if (cdb_dev && cdb_dev->enabled) {
siblings = pci_read_config32(cdb_dev, 0x84);
siblings &= 0xFF;

2
src/northbridge/amd/pi/00730F01/dimmSpd.c
View File

@ -27,7 +27,7 @@
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
{
int spdAddress;
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
DEVTREE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info;
if ((dev == 0) || (config == 0))

18
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -104,7 +104,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
return pcidev_on_root(CONFIG_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@ -581,7 +581,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
uint8_t *p;
acpi_ivrs_t *ivrs_agesa;
struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *nb_dev = pcidev_on_root(0x0, 0);
if (!nb_dev) {
printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__);
@ -786,12 +786,12 @@ static void fam16_finalize(void *chip_info)
{
struct device *dev;
u32 value;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xF8, 0);
pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
/* disable No Snoop */
dev = dev_find_slot(0, PCI_DEVFN(1, 1));
dev = pcidev_on_root(1, 1);
value = pci_read_config32(dev, 0x60);
value &= ~(1 << 11);
pci_write_config32(dev, 0x60, value);
@ -1090,7 +1090,7 @@ static void cpu_bus_scan(struct device *dev)
printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics);
dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
dev_mc = pcidev_on_root(CONFIG_CDB, 0);
if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
die("");
@ -1119,7 +1119,7 @@ static void cpu_bus_scan(struct device *dev)
pbus = dev_mc->bus;
/* Find the cpu's pci device */
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
cdb_dev = pcidev_on_root(devn, 0);
if (!cdb_dev) {
/* If I am probing things in a weird order
* ensure all of the cpu's pci devices are found.
@ -1129,7 +1129,7 @@ static void cpu_bus_scan(struct device *dev)
cdb_dev = pci_probe_dev(NULL, pbus,
PCI_DEVFN(devn, fn));
}
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
cdb_dev = pcidev_on_root(devn, 0);
} else {
/* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned
@ -1142,11 +1142,11 @@ static void cpu_bus_scan(struct device *dev)
family = (family >> 20) & 0xFF;
if (family == 1) { //f10
u32 dword;
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 3));
cdb_dev = pcidev_on_root(devn, 3);
dword = pci_read_config32(cdb_dev, 0xe8);
siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
} else if (family == 7) {//f16
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5));
cdb_dev = pcidev_on_root(devn, 5);
if (cdb_dev && cdb_dev->enabled) {
siblings = pci_read_config32(cdb_dev, 0x84);
siblings &= 0xFF;

2
src/southbridge/amd/pi/hudson/lpc.c
View File

@ -38,7 +38,7 @@ static void lpc_init(struct device *dev)
struct device *sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);

2
src/southbridge/amd/pi/hudson/sd.c
View File

@ -25,7 +25,7 @@ static void sd_init(struct device *dev)
{
u32 stepping;
stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
struct southbridge_amd_pi_hudson_config *sd_chip =
(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);