armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write

Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.

This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.

The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.

Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

src/arch/arm/include/armv7/arch/io.h

@@ -29,40 +29,49 @@
 
 static inline uint8_t read8(const void *addr)
 {
+	uint8_t val;
+
 	dmb();
-	return *(volatile uint8_t *)addr;
+	asm volatile ("ldrb %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }
 
 static inline uint16_t read16(const void *addr)
 {
+	uint16_t val;
+
 	dmb();
-	return *(volatile uint16_t *)addr;
+	asm volatile ("ldrh %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }
 
 static inline uint32_t read32(const void *addr)
 {
+	uint32_t val;
+
 	dmb();
-	return *(volatile uint32_t *)addr;
+	asm volatile ("ldr %0, [%1]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }
 
 static inline void write8(void *addr, uint8_t val)
 {
 	dmb();
-	*(volatile uint8_t *)addr = val;
+	asm volatile ("strb %0, [%1]" : : "r" (val), "r" (addr) : "memory");
 	dmb();
 }
 
 static inline void write16(void *addr, uint16_t val)
 {
 	dmb();
-	*(volatile uint16_t *)addr = val;
+	asm volatile ("strh %0, [%1]" : : "r" (val), "r" (addr) : "memory");
 	dmb();
 }
 
 static inline void write32(void *addr, uint32_t val)
 {
 	dmb();
-	*(volatile uint32_t *)addr = val;
+	asm volatile ("str %0, [%1]" : : "r" (val), "r" (addr) : "memory");
 	dmb();
 }