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Autodetect presence of serial flash and set up the board accordingly. 

This enables us to have only one configuration and one set of code for
all revisions of the Gigabyte GA-M57SLI-S4.
Flash is now setup correctly for both SPI and LPC flash.

Detection of SPI flash in flashrom on rev. 2.x boards now hangs
instead of failing. However, that is just an effect of the combination
of incomplete initialization of the SPI controller and paranoid checks
in the flashrom SPI code.
If anyone wants to work on that, he needs a logic analyzer or creative
imagination. Hint: LPC-to-SPI read passthrough, clock signal.

Remaining issues for the M57SLI: Fan/environment control.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger 2007-11-14 15:09:30 +00:00
parent 31e805dadb
commit 34153ac0b8
2 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/gigabyte/m57sli/Config.lb
View File

@ -310,7 +310,7 @@ chip northbridge/amd/amdk8/root_complex
# SIO pin set 1 input mode # SIO pin set 1 input mode
#irq 0xc8 = 0x0 #irq 0xc8 = 0x0
# SIO pin set 2 mixed input/output mode # SIO pin set 2 mixed input/output mode
irq 0xc9 = 0x0 irq 0xc9 = 0x40
# SIO pin set 4 input mode # SIO pin set 4 input mode
#irq 0xcb = 0x0 #irq 0xcb = 0x0
# Generate SMI# on EC IRQ # Generate SMI# on EC IRQ

17
src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
View File

@ -93,6 +93,7 @@
#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
@ -265,13 +266,27 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0; int needs_reset = 0;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
uint8_t tmp = 0;
if (bist == 0) { if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
} }
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x23, 1); /* The following line will set CLKIN to 24 MHz */
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 1);
tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
/* Is serial flash enabled? Then enable writing to serial flash. */
if (tmp & 0x0e) {
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
pnp_set_logical_device(GPIO_DEV);
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
/* We can get away with not resetting the logical device because
* it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that.
*/
}
it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE); it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_ext_func_mode(SERIAL_DEV);