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soc/amd/stoneyridge: Get rid of domain_read_resources 

The function domain_read_resources() didn't have any code to actually
reserve any resources - it was just creating an empty resource entry.

I looked at fixing it to actually reserve the space, but the values in
the registers at the point when this runs aren't the final values that
we want to reserve anyway, they're temp values with a range much larger
than we want to reserve.

I next looked at moving the amd_initcpuio() function earlier so that we
could get the correct values for the registers, but even that doesn't
give us what we really want.

Ultimately removing this whole function seems to be the right thing.

BUG=None
TEST=Verify that the only resource that changes is the empty resource:
PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080

Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Martin Roth 2018-10-29 16:19:46 -06:00
parent 29f2b258c8
commit 3424f38ae6
2 changed files with 1 additions and 38 deletions
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2
src/soc/amd/stoneyridge/chip.c
View File

@ -114,7 +114,7 @@ const char *soc_acpi_name(const struct device *dev)
};
struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.read_resources = pci_domain_read_resources,
.set_resources = domain_set_resources,
.enable_resources = domain_enable_resources,
.scan_bus = pci_domain_scan_bus,

37
src/soc/amd/stoneyridge/northbridge.c
View File

@ -388,43 +388,6 @@ void fam15_finalize(void *chip_info)
pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);
}
void domain_read_resources(struct device *dev)
{
unsigned int reg;
struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
/* Find the already assigned resource pairs */
for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {
u32 base, limit;
base = pci_read_config32(addr_map, reg);
limit = pci_read_config32(addr_map, reg + 4);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned int nodeid, reg_link;
struct device *reg_dev = dev_find_slot(0, HT_DEVFN);
if (reg < 0xc0) /* mmio */
nodeid = (limit & 0xf) + (base & 0x30);
else /* io */
nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
reg_link = (limit >> 4) & 7;
if (reg_dev) {
/* Reserve the resource */
struct resource *res;
res = new_resource(reg_dev,
IOINDEX(0x1000 + reg,
reg_link));
if (res)
res->flags = 1;
}
}
}
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
pci_domain_read_resources(dev);
}
void domain_enable_resources(struct device *dev)
{
/* Must be called after PCI enumeration and resource allocation */