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mb/google/hatch/vr/puff: Set up PL2 and PsysPL2 

This patch adds correct PL2 baseline setting and PsysPL2 for different
SKUs. There is no way to identify the barral jack power rating, the
assumption is following that ships with the product:
1. i3/i5/i7: 90W BJ
2. Celeron/Pentium: 65W BJ

For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the
original settings as 90% of adapter rating for PsyspL2/PL4 and PL2
as min(PL2, 0.9n) where n is adapter rating power.

BUG=b:143246320
TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Gaggery Tsai 2020-05-19 21:43:42 -07:00 committed by Patrick Georgi
parent be242788c2
commit 342a8c3b2b
1 changed files with 54 additions and 28 deletions
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70
src/mainboard/google/hatch/variants/puff/mainboard.c
View File

@ -4,9 +4,12 @@
#include <chip.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <intelblocks/power_limit.h>
#include <soc/pci_devs.h>
#include <timer.h>
#define GPIO_HDMI_HPD GPP_E13
@ -36,11 +39,10 @@ static void wait_for_hpd(gpio_t gpio, long timeout)
* cable loss and FET Rdson loss in the path from the source.
*/
#define SET_PSYSPL2(w) (9 * (w) / 10)
#define PUFF_PL2 (35)
#define PUFF_PSYSPL2 (58)
#define PUFF_U22_PL2 (35)
#define PUFF_U62_U42_PL2 (51)
#define PUFF_CELERON_PENTIUM_PSYSPL2 (65)
#define PUFF_CORE_CPU_PSYSPL2 (90)
#define PUFF_MAX_TIME_WINDOW 6
#define PUFF_MIN_DUTYCYCLE 4
@ -56,18 +58,15 @@ static void wait_for_hpd(gpio_t gpio, long timeout)
* +-------------+-----+---------+-----------+-------+
* | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
* +-------------+-----+---------+-----------+-------+
* | i7 U42 | 51 | 81 | x(.85PL4) | x(82) |
* | celeron U22 | 35 | 58 | x(.85PL4) | x(51) |
* | i7 U42 | 51 | 90 | x(.85PL4) | x(82) |
* | i3 U22 | 35 | 65 | x(.85PL4) | x(51) |
* +-------------+-----+---------+-----------+-------+
* For USB C charger:
* +-------------+-----+---------+---------+-------+
* +-------------+-----------------+---------+---------+-------+
* | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
* +-------------+-----+---------+---------+-------+
* | 60 (U42) | 44 | 54 | 54 | 54 |
* | 60 (U22) | 29 | 54 | 54 | x(43) |
* | n (U42) | 44 | .9n | .9n | .9n |
* | n (U22) | 29 | .9n | .9n | x(43) |
* +-------------+-----+---------+---------+-------+
* +-------------+-----+-----------+---------+---------+-------+
* | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n |
* +-------------+-----+-----------+---------+---------+-------+
*/
/*
@ -92,9 +91,15 @@ static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
enum usb_chg_type type;
u32 watts;
u16 volts_mv, current_ma;
u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value
u32 pl2 = PUFF_U22_PL2; // default PL2 for U22
int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
dev = pcidev_path_on_root(SA_DEVFN_IGD);
u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
/* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
conf->tdp_psyspl3 = 0;
conf->tdp_pl4 = 0;
@ -102,23 +107,44 @@ static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
if (rv == 0 && type == USB_CHG_TYPE_PD) {
/* Detected USB-PD. Base on max value of adapter */
watts = ((u32)current_ma * volts_mv) / 1000000;
psyspl2 = watts;
conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
/* set psyspl2 to 90% of adapter rating */
psyspl2 = SET_PSYSPL2(watts);
/* Limit PL2 if the adapter is with lower capability */
if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT ||
mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2)
pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2;
else
pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2;
conf->tdp_psyspl3 = psyspl2;
/* set max possible time window */
conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
/* set minimum duty cycle */
conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
/* No data about an arbitrary Type-C adapter, set pl4 conservatively. */
conf->tdp_pl4 = psyspl2;
} else {
/* Input type is barrel jack */
/*
* Input type is barrel jack, from the SKU matrix:
* 1. i3/i5/i7 SKUs use 90W BJ
* 2. Celeron and Pentium use 65W BJ (default)
*/
volts_mv = BJ_VOLTS_MV;
/* Use IGD ID to check if CPU is Core SKUs */
if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 &&
igd_id != PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5) {
psyspl2 = PUFF_CORE_CPU_PSYSPL2;
if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT ||
mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2)
pl2 = PUFF_U62_U42_PL2;
}
}
/* voltage unit is milliVolts and current is in milliAmps */
conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
conf->tdp_pl2_override = PUFF_PL2;
/* set psyspl2 to 90% of max adapter power */
conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
conf->tdp_pl2_override = pl2;
conf->tdp_psyspl2 = psyspl2;
}
void variant_ramstage_init(void)