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southbridge/hudson: Use MMIO instead of PIO to access PM space 

The MMIO region is set up by AGESA very early on, so we can use it to
access the PM register space in ramstage. 16-bit accessors are also
provided to simplify some setup tasks. 16-bit accesses are not
possible via PIO.
The pm2_iowrite/read accessors are removed, as they are not used.

Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5503
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2014-04-14 16:44:19 -05:00
parent f3e82f7969
commit 342ac64a5d
9 changed files with 62 additions and 81 deletions
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8
src/mainboard/amd/olivehill/mptable.c
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@ -96,10 +96,10 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
dword = pm_read8(0x34) & 0xF0;
dword |= (pm_read8(0x35) & 0xFF) << 8;
dword |= (pm_read8(0x36) & 0xFF) << 16;
dword |= (pm_read8(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);

8
src/mainboard/amd/parmer/mptable.c
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@ -96,10 +96,10 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
dword = pm_read8(0x34) & 0xF0;
dword |= (pm_read8(0x35) & 0xFF) << 8;
dword |= (pm_read8(0x36) & 0xFF) << 16;
dword |= (pm_read8(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);

8
src/mainboard/amd/thatcher/mptable.c
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@ -96,10 +96,10 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
dword = pm_read8(0x34) & 0xF0;
dword |= (pm_read8(0x35) & 0xFF) << 8;
dword |= (pm_read8(0x36) & 0xFF) << 16;
dword |= (pm_read8(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);

8
src/mainboard/asrock/imb-a180/mptable.c
View File

@ -96,10 +96,10 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
dword = pm_read8(0x34) & 0xF0;
dword |= (pm_read8(0x35) & 0xFF) << 8;
dword |= (pm_read8(0x36) & 0xFF) << 16;
dword |= (pm_read8(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);

8
src/mainboard/asus/f2a85-m/mptable.c
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@ -95,10 +95,10 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
dword = pm_read8(0x34) & 0xF0;
dword |= (pm_read8(0x35) & 0xFF) << 8;
dword |= (pm_read8(0x36) & 0xFF) << 16;
dword |= (pm_read8(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);

8
src/mainboard/hp/pavilion_m6_1035dx/mptable.c
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@ -96,10 +96,10 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
dword = pm_read8(0x34) & 0xF0;
dword |= (pm_read8(0x35) & 0xFF) << 8;
dword |= (pm_read8(0x36) & 0xFF) << 16;
dword |= (pm_read8(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);

22
src/southbridge/amd/agesa/hudson/fadt.c
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@ -69,23 +69,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */
fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */
pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
pm_write16(0x60, ACPI_PM_EVT_BLK);
pm_write16(0x62, ACPI_PM1_CNT_BLK);
pm_write16(0x64, ACPI_PM_TMR_BLK);
pm_write16(0x68, ACPI_GPE0_BLK);
/* CpuControl is in \_PR.CPU0, 6 bytes */
pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
pm_write16(0x66, ACPI_CPU_CONTROL);
pm_write16(0x6A, 0); /* AcpiSmiCmd */
pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
pm_write8(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at
* index 60-6B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/

59
src/southbridge/amd/agesa/hudson/hudson.c
View File

@ -30,6 +30,13 @@
#include "hudson.h"
#include "smbus.h"
/* Offsets from ACPI_MMIO_BASE
* This is defined by AGESA, but we don't include AGESA headers to avoid
* polluting the namesace.
*/
#define PM_MMIO_BASE 0xfed80300
#if CONFIG_HAVE_ACPI_RESUME
int acpi_get_sleep_type(void)
{
@ -64,39 +71,26 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
}
}
static void pmio_write_index(u16 port_base, u8 reg, u8 value)
void pm_write8(u8 reg, u8 value)
{
outb(reg, port_base);
outb(value, port_base + 1);
write8(PM_MMIO_BASE + reg, value);
}
static u8 pmio_read_index(u16 port_base, u8 reg)
u8 pm_read8(u8 reg)
{
outb(reg, port_base);
return inb(port_base + 1);
return read8(PM_MMIO_BASE + reg);
}
void pm_iowrite(u8 reg, u8 value)
void pm_write16(u8 reg, u16 value)
{
pmio_write_index(PM_INDEX, reg, value);
write16(PM_MMIO_BASE + reg, value);
}
u8 pm_ioread(u8 reg)
u16 pm_read16(u16 reg)
{
return pmio_read_index(PM_INDEX, reg);
return read16(PM_MMIO_BASE + reg);
}
void pm2_iowrite(u8 reg, u8 value)
{
pmio_write_index(PM2_INDEX, reg, value);
}
u8 pm2_ioread(u8 reg)
{
return pmio_read_index(PM2_INDEX, reg);
}
void hudson_enable(device_t dev)
{
printk(BIOS_DEBUG, "hudson_enable()\n");
@ -107,24 +101,21 @@ void hudson_enable(device_t dev)
device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7));
u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16;
/* turn off the SDHC controller in the PM reg */
u8 sd_tmp;
u8 reg8;
if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) {
outb(0xE7, PM_INDEX);
sd_tmp = inb(PM_DATA);
sd_tmp &= ~(1 << 0);
outb(sd_tmp, PM_DATA);
reg8 = pm_read8(0xe7);
reg8 &= ~(1 << 0);
pm_write8(0xe7, reg8);
}
else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) {
outb(0xE8, PM_INDEX);
sd_tmp = inb(PM_DATA);
sd_tmp &= ~(1 << 0);
outb(sd_tmp, PM_DATA);
reg8 = pm_read8(0xe8);
reg8 &= ~(1 << 0);
pm_write8(0xe8, reg8);
}
/* remove device 0:14.7 from PCI space */
outb(0xD3, PM_INDEX);
sd_tmp = inb(PM_DATA);
sd_tmp &= ~(1 << 6);
outb(sd_tmp, PM_DATA);
reg8 = pm_read8(0xd3);
reg8 &= ~(1 << 6);
pm_write8(0xd3, reg8);
}
break;
default:

14
src/southbridge/amd/agesa/hudson/hudson.h
View File

@ -29,8 +29,6 @@
#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
#define HUDSON_ACPI_IO_BASE 0x800
@ -40,12 +38,6 @@
#define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
void pm_iowrite(u8 reg, u8 value);
u8 pm_ioread(u8 reg);
void pm2_iowrite(u8 reg, u8 value);
u8 pm2_ioread(u8 reg);
void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
#define REV_HUDSON_A11 0x11
#define REV_HUDSON_A12 0x12
@ -57,6 +49,12 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr;
#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
void pm_write8(u8 reg, u8 value);
u8 pm_read8(u8 reg);
void pm_write16(u8 reg, u16 value);
u16 pm_read16(u16 reg);
void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
#ifdef __PRE_RAM__
void hudson_lpc_port80(void);
void hudson_pci_port80(void);