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soc/common/intel: Reset is not dependend upon FSP 

Remove dependency of common reset code on FSP

BRANCH=none
BUG=None
TEST=Build and run on Braswell and Skylake

Original-Change-Id: I00052f29326f691b6d56d2349f99815cafff5848
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286932
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I7f59f0aad7dfae92df28cf20fff2d5a684795d22
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11165
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Lee Leahy 2015-07-20 17:24:44 -07:00 committed by Aaron Durbin
parent aa44dbd364
commit 3432e556f5
1 changed files with 0 additions and 1 deletions
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src/soc/intel/common/Kconfig
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@ -66,7 +66,6 @@ config SOC_INTEL_COMMON_FSP_ROMSTAGE
config SOC_INTEL_COMMON_RESET config SOC_INTEL_COMMON_RESET
bool bool
default n default n
depends on PLATFORM_USES_FSP1_1
config SOC_INTEL_COMMON_STACK config SOC_INTEL_COMMON_STACK
bool bool