GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option 

Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will
be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this
in PSP.

BUG=b:200578885, b:202397678
BRANCH=None
TEST=Verstage runs during s0i3 resume on Nipperkin

Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Rob Barnes 2021-12-10 14:28:21 -07:00 committed by Felix Held
parent 941239d54d
commit 3437a6fbb0
2 changed files with 13 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/amd/cezanne/Makefile.inc
View File

@ -110,6 +110,10 @@ else
PSP_SOFTFUSE_BITS += 29
endif
ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y)
PSP_SOFTFUSE_BITS += 40
endif
# Use additional Soft Fuse bits specified in Kconfig
PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS))

11
src/soc/amd/common/psp_verstage/Kconfig
View File

@ -6,10 +6,17 @@ config PSP_VERSTAGE_CCP_DMA
accessing the boot device. Select it on platforms which supports
using CCP DMA to access the boot device.
config PSP_S0I3_RESUME_VERSTAGE
bool "S0i3 resume verstage"
depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
default n
help
Select this item to enable running verstage during S0i3 resume.
config PSP_INIT_TPM_ON_S0I3_RESUME
bool
depends on TPM2 && VBOOT_STARTS_BEFORE_BOOTBLOCK
default VBOOT_STARTS_BEFORE_BOOTBLOCK
depends on TPM2 && PSP_S0I3_RESUME_VERSTAGE
default PSP_S0I3_RESUME_VERSTAGE
help
If the TPM is reset while in S0i3, it must be reinitialized
during s0i3 resume. This must be performed in PSP verstage since