GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/xeon_sp: Modify FSP-T code caching parameters 

Use CACHE_ROM_BASE and CACHE_ROM_SIZE for code caching
parameters.

Tested on OCP Tioga Pass.

Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39625
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johnny Lin 2020-03-18 10:23:26 +08:00 committed by Andrey Petrov
parent e82b02c004
commit 34473ea6c9
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/intel/xeon_sp/bootblock/bootblock.c
View File

@ -19,6 +19,7 @@
#include <intelblocks/fast_spi.h>
#include <soc/iomap.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
const FSPT_UPD temp_ram_init_params = {
.FspUpdHeader = {
@ -29,8 +30,8 @@ const FSPT_UPD temp_ram_init_params = {
.FsptCoreUpd = {
.MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
.MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
.CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
.CodeRegionBase = (UINT32)CACHE_ROM_BASE,
.CodeRegionLength = (UINT32)CACHE_ROM_SIZE,
.Reserved1 = {0},
},
.FsptConfig = {