diff --git a/src/northbridge/intel/sandybridge/hostbridge_regs.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h
similarity index 91%
rename from src/northbridge/intel/sandybridge/hostbridge_regs.h
rename to src/northbridge/intel/sandybridge/registers/host_bridge.h
index 2d2fcff3b1..4814b94b6f 100644
--- a/src/northbridge/intel/sandybridge/hostbridge_regs.h
+++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __SANDYBRIDGE_HOSTBRIDGE_REGS_H__
-#define __SANDYBRIDGE_HOSTBRIDGE_REGS_H__
+#ifndef __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__
+#define __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__
 
 #define EPBAR		0x40
 #define MCHBAR		0x48
@@ -60,4 +60,4 @@
 
 #define DIDOR		0xf3	/* Device ID override, for debug and samples only */
 
-#endif /* __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ */
+#endif /* __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ */
diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/registers/mchbar.h
similarity index 99%
rename from src/northbridge/intel/sandybridge/mchbar_regs.h
rename to src/northbridge/intel/sandybridge/registers/mchbar.h
index 370dd74381..2fe6b24e76 100644
--- a/src/northbridge/intel/sandybridge/mchbar_regs.h
+++ b/src/northbridge/intel/sandybridge/registers/mchbar.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__
-#define __SANDYBRIDGE_MCHBAR_REGS_H__
+#ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__
+#define __SANDYBRIDGE_REGISTERS_MCHBAR_H__
 
 /*
  * ### IOSAV memory controller interface poking state machine notes ###
@@ -533,4 +533,4 @@
 #define CRDTCTL4		0x7410 /* Read Return Tracker credits */
 #define CRDTLCK			0x77fc
 
-#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */
+#endif /* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 5318d0b245..5c15cb1ad3 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -36,7 +36,7 @@ enum platform_type {
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 #define HOST_BRIDGE	PCI_DEV(0, 0, 0)
 
-#include "hostbridge_regs.h"
+#include "registers/host_bridge.h"
 
 
 /* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */
@@ -66,7 +66,7 @@ enum platform_type {
 #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
 
 /* As there are many registers, define them on a separate file */
-#include "mchbar_regs.h"
+#include "registers/mchbar.h"
 
 /*
  * EPBAR - Egress Port Root Complex Register Block