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sb/intel/common: Properly guard USB debug 

The declarations in usb_debug.c needs to be guarded in order to not
conflict with other chipsets.

Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36878
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-16 10:04:41 +01:00 committed by Patrick Georgi
parent dc2e7c6e0f
commit 3457df1730
10 changed files with 15 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/southbridge/intel/bd82x6x/Kconfig
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@ -47,6 +47,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR
hex

4
src/southbridge/intel/common/Kconfig
View File

@ -46,6 +46,10 @@ config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
bool
config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
def_bool n
select HAVE_USBDEBUG
config INTEL_DESCRIPTOR_MODE_CAPABLE
def_bool n
help

6
src/southbridge/intel/common/Makefile.inc
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@ -28,9 +28,9 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
bootblock-$(CONFIG_USBDEBUG) += usb_debug.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c

2
src/southbridge/intel/fsp_rangeley/Kconfig
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@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
@ -34,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR
hex

2
src/southbridge/intel/i82801dx/Kconfig
View File

@ -19,10 +19,10 @@ config SOUTHBRIDGE_INTEL_I82801DX
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE

2
src/southbridge/intel/i82801gx/Kconfig
View File

@ -17,7 +17,6 @@ config SOUTHBRIDGE_INTEL_I82801GX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select COMMON_FADT
@ -33,6 +32,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801GX

2
src/southbridge/intel/i82801ix/Kconfig
View File

@ -23,7 +23,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select IOAPIC
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
@ -33,6 +32,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
select INTEL_DESCRIPTOR_MODE_CAPABLE
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801IX

2
src/southbridge/intel/i82801jx/Kconfig
View File

@ -24,7 +24,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select IOAPIC
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
@ -36,6 +35,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801JX

2
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -22,7 +22,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_USBDEBUG
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
@ -45,6 +44,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR
hex

1
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -45,6 +45,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config INTEL_LYNXPOINT_LP
bool