sb/intel/common: Properly guard USB debug
The declarations in usb_debug.c needs to be guarded in order to not conflict with other chipsets. Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36878 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -47,6 +47,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_COMMON_SMM
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select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
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select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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config EHCI_BAR
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hex
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@ -46,6 +46,10 @@ config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
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config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
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bool
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config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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def_bool n
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select HAVE_USBDEBUG
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config INTEL_DESCRIPTOR_MODE_CAPABLE
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def_bool n
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help
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@ -28,9 +28,9 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c
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all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
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smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
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bootblock-$(CONFIG_USBDEBUG) += usb_debug.c
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romstage-$(CONFIG_USBDEBUG) += usb_debug.c
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ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
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bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
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bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select IOAPIC
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select HAVE_USBDEBUG
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select USE_WATCHDOG_ON_BOOT
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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@ -34,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_COMMON_PMBASE
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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config EHCI_BAR
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hex
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@ -19,10 +19,10 @@ config SOUTHBRIDGE_INTEL_I82801DX
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select IOAPIC
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select HAVE_SMI_HANDLER
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select HAVE_USBDEBUG
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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@ -17,7 +17,6 @@ config SOUTHBRIDGE_INTEL_I82801GX
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bool
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select IOAPIC
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select HAVE_USBDEBUG
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select USE_WATCHDOG_ON_BOOT
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select HAVE_SMI_HANDLER
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select COMMON_FADT
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@ -33,6 +32,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
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select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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if SOUTHBRIDGE_INTEL_I82801GX
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@ -23,7 +23,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select IOAPIC
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select HAVE_USBDEBUG
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select USE_WATCHDOG_ON_BOOT
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select HAVE_SMI_HANDLER
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select HAVE_USBDEBUG_OPTIONS
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@ -33,6 +32,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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if SOUTHBRIDGE_INTEL_I82801IX
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@ -24,7 +24,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select IOAPIC
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select HAVE_USBDEBUG
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select USE_WATCHDOG_ON_BOOT
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select HAVE_SMI_HANDLER
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select HAVE_USBDEBUG_OPTIONS
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@ -36,6 +35,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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if SOUTHBRIDGE_INTEL_I82801JX
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@ -22,7 +22,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select IOAPIC
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select HAVE_USBDEBUG
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select HAVE_SMI_HANDLER
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select USE_WATCHDOG_ON_BOOT
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select PCIEXP_ASPM
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@ -45,6 +44,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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config EHCI_BAR
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hex
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@ -45,6 +45,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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config INTEL_LYNXPOINT_LP
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bool
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