mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
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5e60637ef6
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34672f2bc4
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@ -16,10 +16,6 @@ chip soc/intel/broadwell
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register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
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# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
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register "gen1_dec" = "0x00000381"
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register "gen2_dec" = "0x000c0081"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -27,33 +23,40 @@ chip soc/intel/broadwell
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 off end # Serial I/O DMA
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device pci 15.1 off end # I2C0
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device pci 15.2 off end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3 - LAN
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device pci 1c.3 on end # PCIe Port #4 - WiFi
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device pci 1c.4 on end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
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device pci 1d.0 off end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus
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device pci 1f.6 off end # Thermal
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# chip soc/intel/broadwell/pch
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# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
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register "gen1_dec" = "0x00000381"
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register "gen2_dec" = "0x000c0081"
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 off end # Serial I/O DMA
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device pci 15.1 off end # I2C0
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device pci 15.2 off end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3 - LAN
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device pci 1c.3 on end # PCIe Port #4 - WiFi
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device pci 1c.4 on end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
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device pci 1d.0 off end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus
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device pci 1f.6 off end # Thermal
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# end
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end
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end
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@ -1,14 +1,16 @@
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chip soc/intel/broadwell
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# Port 0 is HDD
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# Port 3 is M.2 NGFF
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register "sata_port_map" = "0x9"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "9"
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register "sata_port3_gen3_dtle" = "9"
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device domain 0 on
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device pci 1c.2 on end # PCIe Port #3 - LAN
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# chip soc/intel/broadwell/pch
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# Port 0 is HDD
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# Port 3 is M.2 NGFF
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register "sata_port_map" = "0x9"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "9"
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register "sata_port3_gen3_dtle" = "9"
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device pci 1c.2 on end # PCIe Port #3 - LAN
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# end
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end
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end
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@ -1,14 +1,16 @@
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chip soc/intel/broadwell
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# Port 0 is HDD
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# Port 1 is M.2 NGFF
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register "sata_port_map" = "0x3"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "7"
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register "sata_port1_gen3_dtle" = "9"
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device domain 0 on
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device pci 1d.0 on end # USB2 EHCI
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# chip soc/intel/broadwell/pch
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# Port 0 is HDD
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# Port 1 is M.2 NGFF
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register "sata_port_map" = "0x3"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "7"
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register "sata_port1_gen3_dtle" = "9"
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device pci 1d.0 on end # USB2 EHCI
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# end
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end
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end
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