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drivers/intel/fsp1_1: Use C over CPP 

This fixes building with clang.

Change-Id: Ida464d9ff96af3ff485682fbbf904bb2253ec44f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2022-03-24 00:26:57 +01:00
parent 25a0c67e9d
commit 3473d16640
1 changed files with 19 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/drivers/intel/fsp1_1/fsp_util.c
View File

@ -89,26 +89,26 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
(u8)((fsp_header->ImageRevision >> 16) & 0xff),
(u8)((fsp_header->ImageRevision >> 8) & 0xff),
(u8)(fsp_header->ImageRevision & 0xff));
#if CONFIG(DISPLAY_FSP_ENTRY_POINTS)
printk(BIOS_SPEW, "FSP Entry Points:\n");
printk(BIOS_SPEW, " %p: Image Base\n", fsp_base);
printk(BIOS_SPEW, " %p: TempRamInit\n",
&fsp_base[fsp_header->TempRamInitEntryOffset]);
printk(BIOS_SPEW, " %p: FspInit\n",
&fsp_base[fsp_header->FspInitEntryOffset]);
if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
printk(BIOS_SPEW, " %p: MemoryInit\n",
&fsp_base[fsp_header->FspMemoryInitEntryOffset]);
printk(BIOS_SPEW, " %p: TempRamExit\n",
&fsp_base[fsp_header->TempRamExitEntryOffset]);
printk(BIOS_SPEW, " %p: SiliconInit\n",
&fsp_base[fsp_header->FspSiliconInitEntryOffset]);
if (CONFIG(DISPLAY_FSP_ENTRY_POINTS)) {
printk(BIOS_SPEW, "FSP Entry Points:\n");
printk(BIOS_SPEW, " %p: Image Base\n", fsp_base);
printk(BIOS_SPEW, " %p: TempRamInit\n",
&fsp_base[fsp_header->TempRamInitEntryOffset]);
printk(BIOS_SPEW, " %p: FspInit\n",
&fsp_base[fsp_header->FspInitEntryOffset]);
if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
printk(BIOS_SPEW, " %p: MemoryInit\n",
&fsp_base[fsp_header->FspMemoryInitEntryOffset]);
printk(BIOS_SPEW, " %p: TempRamExit\n",
&fsp_base[fsp_header->TempRamExitEntryOffset]);
printk(BIOS_SPEW, " %p: SiliconInit\n",
&fsp_base[fsp_header->FspSiliconInitEntryOffset]);
}
printk(BIOS_SPEW, " %p: NotifyPhase\n",
&fsp_base[fsp_header->NotifyPhaseEntryOffset]);
printk(BIOS_SPEW, " %p: Image End\n",
&fsp_base[fsp_header->ImageSize]);
}
printk(BIOS_SPEW, " %p: NotifyPhase\n",
&fsp_base[fsp_header->NotifyPhaseEntryOffset]);
printk(BIOS_SPEW, " %p: Image End\n",
&fsp_base[fsp_header->ImageSize]);
#endif
}
void fsp_notify(u32 phase)