soc/intel/common: Add whiskeylake celeron v-0 support

New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/include/device/pci_ids.h

@@ -2969,6 +2969,7 @@
 #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500		0x5a85
 #define PCI_DEVICE_ID_INTEL_GLK_IGD			0x3184
 #define PCI_DEVICE_ID_INTEL_GLK_IGD_EU12		0x3185
+#define PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1		0x3EA1
 #define PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1		0x3EA0
 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1		0x5A51
 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2		0x5A59

src/soc/intel/cannonlake/bootblock/report_platform.c

@@ -37,6 +37,7 @@ static struct {
 	{ CPUID_CANNONLAKE_C0, "Cannonlake C0" },
 	{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
 	{ CPUID_COFFEELAKE_D0, "Coffeelake D0" },
+	{ CPUID_WHISKEYLAKE_V0, "Whiskeylake V0"},
 	{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},
 	{ CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },
 };

src/soc/intel/common/block/cpu/mp_init.c

@@ -70,6 +70,7 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 },
 	{ X86_VENDOR_INTEL, CPUID_GLK_A0 },
 	{ X86_VENDOR_INTEL, CPUID_GLK_B0 },
+	{ X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 },
 	{ X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 },
 	{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 },
 	{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 },

src/soc/intel/common/block/graphics/graphics.c

@@ -118,6 +118,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,
 	PCI_DEVICE_ID_INTEL_GLK_IGD,
 	PCI_DEVICE_ID_INTEL_GLK_IGD_EU12,
+	PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1,
 	PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1,
 	PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM,
 	PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM,

src/soc/intel/common/block/include/intelblocks/mp_init.h

@@ -37,6 +37,7 @@
 #define CPUID_APOLLOLAKE_E0	0x506ca
 #define CPUID_GLK_A0		0x706a0
 #define CPUID_GLK_B0		0x706a1
+#define CPUID_WHISKEYLAKE_V0	0x806ec
 #define CPUID_WHISKEYLAKE_W0	0x806eb
 #define CPUID_COFFEELAKE_D0	0x806ea
 #define CPUID_COFFEELAKE_U0	0x906ea