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cpu/intel/car: Align the stack to 16 bytes before romstage_main 

Change-Id: I1415c18779bc481fdec5f72f83c06a58ce6d5c39
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26797
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-06-03 17:14:19 +02:00 committed by Patrick Georgi
parent 995b99d996
commit 348b79f057
3 changed files with 13 additions and 0 deletions
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4
src/cpu/intel/car/core2/cache_as_ram.S
View File

@ -169,6 +169,10 @@ addrsize_set_high:
/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
/* Align the stack 16 bytes */
andl $0xfffffff0, %esp
/* Account for pushing the BIST result */
subl $12, %esp
/* Restore the BIST result. */
movl %ebp, %eax

5
src/cpu/intel/car/non-evict/cache_as_ram.S
View File

@ -174,6 +174,11 @@ addrsize_set_high:
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
/* Align the stack 16 bytes */
andl $0xfffffff0, %esp
/* Account for pushing the BIST result */
subl $12, %esp
/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp

4
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -355,6 +355,10 @@ skip_cache_rom:
/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
/* Align the stack 16 bytes */
andl $0xfffffff0, %esp
/* Account for pushing the BIST result */
subl $12, %esp
/* Restore the BIST result. */
movl %ebp, %eax