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mb/intel/tglrvp: Update display ports for RVP 

Enable DdiPortBHpd and additional pin muxes for DPs.  These pin muxes
were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port
pin mux from pinctl driver.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-03-02 22:18:26 -08:00 committed by Patrick Georgi
parent dd3604422f
commit 34944be317
2 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -52,6 +52,7 @@ chip soc/intel/tigerlake
# enabling EDP in PortA
register "DdiPortAConfig" = "1"
register "DdiPortBHpd" = "1"
register "DdiPort1Hpd" = "1"
register "DdiPort1Ddc" = "1"

10
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
View File

@ -61,7 +61,6 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/*Audio */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */
@ -83,6 +82,15 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
/* DP */
PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */
PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */
PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */
PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */
PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */
PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */
PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */
PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */
};
const struct pad_config *variant_gpio_table(size_t *num)