diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 21263b99b9..476872404e 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -51,6 +51,18 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if HAVE_ACPI_TABLES + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb +end + if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index fa38f84a0b..d8ffb3d11c 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -30,6 +30,12 @@ uses USE_OPTION_TABLE uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES +uses CONFIG_MULTIBOOT +uses HAVE_SMI_HANDLER uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR @@ -54,6 +60,7 @@ uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA +uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -77,11 +84,7 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK ## ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default ROM_SIZE=524288 - -#1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=512*1024 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use @@ -104,6 +107,11 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 +## +## Build SMI handler +## +default HAVE_SMI_HANDLER=0 + ## ## Build code to export a programmable irq routing table ## @@ -116,6 +124,15 @@ default IRQ_SLOT_COUNT=11 ## default HAVE_MP_TABLE=1 +## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 +default HAVE_LOW_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=0 +default CONFIG_MULTIBOOT=0 + ## ## Build code to export a CMOS option table ## @@ -128,6 +145,11 @@ default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 default LB_CKS_LOC=123 +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 + ## ## Build code for SMP support ## Only worry about 2 micro processors diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c new file mode 100644 index 0000000000..cc3b5c2364 --- /dev/null +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -0,0 +1,180 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + apic_addr, 0); + } + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk_debug("ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk_debug("ACPI: * DSDT %p\n", dsdt); + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk_debug("ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk_debug("ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk_debug("ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk_debug("ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk_debug("ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk_debug("ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdt, ssdt); + + printk_info("ACPI: done %p.\n", (void *)current); + return current; +} diff --git a/src/mainboard/tyan/s2891/dsdt.dsl b/src/mainboard/tyan/s2891/dsdt.dsl new file mode 100644 index 0000000000..f6a8505481 --- /dev/null +++ b/src/mainboard/tyan/s2891/dsdt.dsl @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2007, 2008 Rudolf Marek + * + * ISA portions taken from QEMU acpi-dsdt.dsl. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl") + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + /* 2:00 PCIe x4 SB IRQ 17 */ + Device (PE4) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/ + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ + Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Onboard NIC */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, + }) + } + } + } +} diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index d1c7be1b5e..df0f0068e3 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -1,6 +1,22 @@ #include +#include +#include #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + + #if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2891 Mainboard") diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index cf917eeb8e..a03f117325 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -122,8 +122,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); // Onboard ck804 smbus - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); -// 10 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 @@ -137,7 +136,7 @@ void *smp_write_config_table(void *v) // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 -//Slot PCIE x16 +//Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index 4b3f668e50..8663ab698e 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -51,6 +51,18 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if HAVE_ACPI_TABLES + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb +end + if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -218,9 +230,10 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 3 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 37b9b5baa2..67937e0b18 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -30,6 +30,12 @@ uses USE_OPTION_TABLE uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES +uses CONFIG_MULTIBOOT +uses HAVE_SMI_HANDLER uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR @@ -54,6 +60,7 @@ uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA +uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -71,11 +78,7 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK ## ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default ROM_SIZE=524288 - -#1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=1024*1024 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use @@ -98,6 +101,11 @@ default HAVE_FALLBACK_BOOT=1 ## default HAVE_HARD_RESET=1 +## +## Build SMI handler +## +default HAVE_SMI_HANDLER=0 + ## ## Build code to export a programmable irq routing table ## @@ -110,6 +118,15 @@ default IRQ_SLOT_COUNT=11 ## default HAVE_MP_TABLE=1 +## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 +default HAVE_LOW_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=0 +default CONFIG_MULTIBOOT=0 + ## ## Build code to export a CMOS option table ## @@ -122,6 +139,11 @@ default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 default LB_CKS_LOC=123 +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 + ## ## Build code for SMP support ## Only worry about 2 micro processors diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c new file mode 100644 index 0000000000..cc3b5c2364 --- /dev/null +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -0,0 +1,180 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + apic_addr, 0); + } + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk_debug("ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk_debug("ACPI: * DSDT %p\n", dsdt); + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk_debug("ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk_debug("ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk_debug("ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk_debug("ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk_debug("ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk_debug("ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdt, ssdt); + + printk_info("ACPI: done %p.\n", (void *)current); + return current; +} diff --git a/src/mainboard/tyan/s2892/dsdt.dsl b/src/mainboard/tyan/s2892/dsdt.dsl new file mode 100644 index 0000000000..95bd9b9611 --- /dev/null +++ b/src/mainboard/tyan/s2892/dsdt.dsl @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2007, 2008 Rudolf Marek + * + * ISA portions taken from QEMU acpi-dsdt.dsl. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl") + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, /* 1:08 Onboard Intel NIC IRQ 18 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + /* 2:00 PCIe x4 SB IRQ 17 */ + Device (PE4) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1b }, /* PCIE IRQ24-IRQ27 shifted 3*/ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1a }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1b }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Onboard NIC, SO-DIMM, Slot 4 */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x1f }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 2 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1e }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1f }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1c }, + }) + } + } + } +} diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index a1f3e04340..26fb8f0894 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -1,6 +1,22 @@ #include +#include +#include #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + + #if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2892 Mainboard") diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index c46fa9add8..da2daac85e 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -122,8 +122,7 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); // Onboard ck804 smbus - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); -// 10 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 @@ -137,7 +136,7 @@ void *smp_write_config_table(void *v) // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 -//Slot PCIE x16 +//Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } @@ -150,7 +149,7 @@ void *smp_write_config_table(void *v) //Slot 2 PCI 32 for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (4<<2)|i, apicid_ck804, 0x10+(0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16 } diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb index c87a530852..1ac890c00d 100644 --- a/src/mainboard/tyan/s2895/Config.lb +++ b/src/mainboard/tyan/s2895/Config.lb @@ -60,6 +60,18 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if HAVE_ACPI_TABLES + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb +end + if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -254,9 +266,10 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 3 end device pnp 2e.4 on # Com1 io 0x60 = 0x3f8 @@ -282,7 +295,8 @@ chip northbridge/amd/amdk8/root_complex end end device pnp 2e.a on # RT - io 0x60 = 0x400 + io 0x60 = 0x90 + irq 0x70 = 8 end end end diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index 55bef9597c..9949c679a5 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -33,6 +33,12 @@ uses USE_OPTION_TABLE uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES +uses CONFIG_MULTIBOOT +uses HAVE_SMI_HANDLER uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR @@ -56,6 +62,7 @@ uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA +uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK uses K8_HT_FREQ_1G_SUPPORT @@ -80,11 +87,7 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK ## ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default ROM_SIZE=524288 - -#1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=1024*1024 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use @@ -111,6 +114,11 @@ default HAVE_FAILOVER_BOOT=1 ## default HAVE_HARD_RESET=1 +## +## Build SMI handler +## +default HAVE_SMI_HANDLER=0 + ## ## Build code to export a programmable irq routing table ## @@ -123,6 +131,15 @@ default IRQ_SLOT_COUNT=11 ## default HAVE_MP_TABLE=1 +## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 +default HAVE_LOW_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=0 +default CONFIG_MULTIBOOT=0 + ## ## Build code to export a CMOS option table ## @@ -135,6 +152,11 @@ default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 default LB_CKS_LOC=123 +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 + ## ## Build code for SMP support ## Only worry about 2 micro processors diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c new file mode 100644 index 0000000000..5072326455 --- /dev/null +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -0,0 +1,191 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + apic_addr, 0); + } + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* Write second NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, + apic_addr, 0x20); + } + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + /* Doesn't work on this board. */ + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk_debug("ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk_debug("ACPI: * DSDT %p\n", dsdt); + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk_debug("ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk_debug("ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk_debug("ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk_debug("ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk_debug("ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk_debug("ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdt, ssdt); + + printk_info("ACPI: done %p.\n", (void *)current); + return current; +} diff --git a/src/mainboard/tyan/s2895/dsdt.dsl b/src/mainboard/tyan/s2895/dsdt.dsl new file mode 100644 index 0000000000..b449064954 --- /dev/null +++ b/src/mainboard/tyan/s2895/dsdt.dsl @@ -0,0 +1,344 @@ +/* + * This file is part of the coreboot project. + * + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2007, 2008 Rudolf Marek + * + * ISA portions taken from QEMU acpi-dsdt.dsl. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl") + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x14 }, /* 0x2 AUDIO IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x15 }, /* 0xa LAN IRQ 21 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, /* 1:05 IEEE-1394 IRQ 19 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* RTC */ + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0090, 0x02) + IRQNoFlags () {8} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* CK804 2050 */ + Device (PCI1) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x80) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x01, 0x00), BUF0, Local1) + Concatenate (\_SB.GIOR (0x01, 0x00), Local1, Local2) + Concatenate (\_SB.GWBN (0x01, 0x00), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table for this root bus */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x35 }, /* 0xa LAN IRQ 53 */ + }) + + /* PCIe x16 SB2 IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x81) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x32 }, /* PCIE IRQ48-IRQ51 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x33 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x30 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x31 }, + }) + } + + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1a }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1b }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Slot 4, Onboard SCSI, Slot 5 */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1f }, + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x1e }, /* PCIE IRQ28-IRQ31 shifted 2 */ + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x1f }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1c }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 1 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1f }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1c }, + }) + } + } + } +} diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index f615b1fd0a..5f38556467 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -1,6 +1,22 @@ #include +#include +#include #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + + #if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2895 Mainboard") diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index 1591ec9e64..6036cf0c30 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -121,13 +121,13 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base); } - dword = 0x0000d218; + dword = 0x0000d218; // Why does the factory BIOS have 0? pci_write_config32(dev, 0x7c, dword); dword = 0x00000000; pci_write_config32(dev, 0x80, dword); - dword = 0x00000d00; + dword = 0x00000d00; // Same here. pci_write_config32(dev, 0x84, dword); } @@ -171,7 +171,7 @@ void *smp_write_config_table(void *v) // Onboard ck804 NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 -//Slot 1 PCIE x16 +//Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } @@ -181,7 +181,7 @@ void *smp_write_config_table(void *v) //Slot 2 PCI 32 for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16 } if(sysconf.pci1234[2] & 0xf) { diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 5dc8e1f376..e0f5d7975f 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -202,7 +202,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, }, - { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LPC47B397_RT, PNP_IO0 | PNP_IRQ0, { 0x7fc, 0 }, }, }; static void enable_dev(struct device *dev)