soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Able to see TS elapse prior to IA reset on Rex Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Bora Guvendik
Subrata Banik
parent
28ac0fd2f0
commit
34c37bb1c5
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@ -5,6 +5,8 @@
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#if CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1)
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#include "cse_telemetry_v1.h"
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#elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2)
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#include "cse_telemetry_v2.h"
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#endif
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#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H
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@ -0,0 +1,163 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H
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#define SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H
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enum cse_boot_perf_data_v2 {
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/* CSME ROM start execution */
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PERF_DATA_CSME_ROM_START = 0,
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/* EC Boot Load Done (CSME ROM starts main execution) */
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PERF_DATA_EC_BOOT_LOAD_DONE = 1,
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/* CSME ROM completed execution / CSME RBE started */
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PERF_DATA_CSME_ROM_COMPLETED = 2,
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/* CSME got ESE Init Done indication from ESE */
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PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3,
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/* CSME RBE started SOC.PMC patch and payloads read from SPI flash */
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PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_START = 4,
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/* CSME RBE completed SOC.PMC patch and payloads read from SPI flash */
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PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_COMPLETED = 5,
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/* CSME RBE started pushing SOC.PMC patch and payloads */
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PERF_DATA_CSME_RBE_SOC_PMC_PATCH_PUSH_START = 6,
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/* CSME RBE completed pushing SOC.PMC patch and payloads */
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PERF_DATA_CSME_RBE_SOC_PMC_PATCH_PUSH_COMPLETED = 7,
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/* CSME RBE set "Boot Stall Done" indication to SOC.PMC */
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PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 8,
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/* CSME RBE Started load IOE.PMC patch and payloads */
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PERF_DATA_CSME_RBE_IOE_PMC_PATCH_LOADING_START = 9,
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/* CSME RBE completed to load IOE.PMC patch and payloads */
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PERF_DATA_CSME_RBE_IOE_PMC_PATCH_LOADING_COMPLETED = 10,
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/* CSME RBE jumped to CSME Kernel */
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PERF_DATA_CSME_RBE_KERNEL_JUMP = 11,
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/* CSME BUP start running */
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PERF_DATA_CSME_BUP_START = 12,
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/* CSME established IPC channel communication with ESE */
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PERF_DATA_CSME_IPC_CHANNEL_FOR_ESE_UP = 13,
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/* ESE FW initialization completed */
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PERF_DATA_ESE_FW_INIT_DONE = 14,
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/* PMC set PPS */
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PERF_DATA_PMC_SET_PPS = 15,
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/* CSME got ICC_CFG_START message from PMC */
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PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC = 16,
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/* PMC got PCH_PWROK */
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PERF_DATA_PMC_GOT_PCH_PWROK = 17,
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/* CSME set "Host Boot Prep Done" indication to PMC */
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PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 18,
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/* CSME starts PHYs loading - phase 1 - USB, PCIe */
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PERF_DATA_CSME_PHASE1_PHY_LOADING_START = 19,
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/* CSME completed phase 1 PHYs loading - USB, PCIe */
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PERF_DATA_CSME_PHASE1_PHY_LOADING_COMPLETED = 20,
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/* PMC indicated CSME that xxPWRGOOD was asserted */
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PERF_DATA_PMC_PWRGOOD_ASSERTED = 21,
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/* PMC indicated CSME that SYS_PWROK was asserted */
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PERF_DATA_PMC_SYS_PWROK_ASSERTED = 22,
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/* ESE sent IPC message to CSME indicating PUnit load completed */
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PERF_DATA_ESE_PUNIT_LOAD_COMPLETED = 23,
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/* PMC indicates CSME that xxPLTRST was de-asserted */
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PERF_DATA_PMC_PLTRST_DEASSERTED = 24,
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/* PMC sent "CPU_BOOT_CONFIG" start message to CSME */
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PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 25,
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/* CSME starts PHYs loading - phase 2 - UFS */
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PERF_DATA_CSME_PHASE2_PHY_LOADING_START = 26,
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/* CSME completed phase 2 PHYs loading - UFS */
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PERF_DATA_CSME_PHASE2_PHY_LOADING_COMPLETED = 27,
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/* CSME sent "CPU_BOOT_CONFIG" done message to PMC */
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PERF_DATA_CSME_CPU_BOOT_CONFIG_DONE = 28,
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/* PMC sent "Core Reset Done Ack - Sent" message to CSME */
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PERF_DATA_PMC_SENT_CRDA = 29,
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/* ESE sent IPC message to CSME indicating DMU load completed */
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PERF_DATA_ESE_DMU_LOAD_COMPLETED = 30,
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/* ACM Active indication - ACM started its execution */
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PERF_DATA_ACM_START = 31,
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/* ACM Done indication - ACM completed execution */
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PERF_DATA_ACM_DONE = 32,
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/* BIOS sent "Get_BIOS_Seed" message to CSME */
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PERF_DATA_BIOS_SEED_MSG_RECEIVED = 33,
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/* CSME responded to "Get_BIOS_Seed" message */
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PERF_DATA_BIOS_SEED_MSG_REPLIED = 34,
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/* BIOS sent DRAM Init Done message */
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PERF_DATA_BIOS_DRAM_INIT_DONE = 35,
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/* CSME sent DRAM Init Done message back to BIOS */
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PERF_DATA_CSME_DRAM_INIT_DONE = 36,
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/* CSME started loading TCSS components (IOM, NPHY, TBT) */
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PERF_DATA_CSME_LOAD_TCSS_START = 37,
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/* CSME start loading ACE */
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PERF_DATA_CSME_LOAD_ACE_START = 38,
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/* CSME started loading eDP PHY */
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PERF_DATA_CSME_LOAD_EDP_PHY_START = 39,
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/* CSME completed loading eDP PHY */
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PERF_DATA_CSME_LOAD_EDP_PHY_COMPLETED = 40,
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/* BIOS sent "Core BIOS Done" message to CSME */
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PERF_DATA_BIOS_BIOS_CORE_DONE = 41,
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/* CSME sent "Core BIOS Done" ack message back to BIOS */
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PERF_DATA_CSME_BIOS_CORE_DONE = 42,
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/* BIOS sent "End Of Post" message to CSME */
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PERF_DATA_BIOS_END_OF_POST = 43,
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/* CSME sent "End Of Post" ack message back to BIOS */
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PERF_DATA_CSME_END_OF_POST = 44,
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/* CSME started loading ISH Bringup module */
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PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 45,
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/* CSME completed loading ISH Bringup module */
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PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 46,
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/* CSME started loading ISH Main module */
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PERF_DATA_CSME_LOAD_ISH_MAIN_START = 47,
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/* CSME completed loading Main module */
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PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 48,
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/* CSME reached Transition Complete */
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PERF_DATA_CSME_TRANSITION_COMPLETE = 49,
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/* 50 - 62 Reserved */
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/* Timestamp when CSME responded to BupGetBootData message itself */
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PERF_DATA_CSME_GET_PERF_RESPONSE = 63,
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};
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#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H
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@ -21,6 +21,7 @@ bootblock-y += espi.c
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bootblock-y += p2sb.c
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bootblock-y += soc_info.c
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romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
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romstage-y += espi.c
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romstage-y += meminit.c
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romstage-y += pcie_rp.c
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@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <console/console.h>
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#include <intelblocks/cse.h>
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#include <timestamp.h>
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void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time)
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{
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s64 start_stamp;
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if (!ts) {
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printk(BIOS_ERR, "%s: Failed to insert CSME timestamps\n", __func__);
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return;
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}
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start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE];
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timestamp_add(TS_ME_ROM_START, start_stamp);
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timestamp_add(TS_ME_BOOT_STALL_END,
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start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]);
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timestamp_add(TS_ME_ICC_CONFIG_START,
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start_stamp + ts[PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC]);
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timestamp_add(TS_ME_HOST_BOOT_PREP_END,
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start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]);
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timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC,
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start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]);
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timestamp_add(TS_ESE_DMU_LOAD_END,
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start_stamp + ts[PERF_DATA_ESE_DMU_LOAD_COMPLETED]);
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}
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@ -134,6 +134,10 @@ void mainboard_romstage_entry(void)
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timestamp_add_now(TS_CSE_FW_SYNC_END);
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}
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/* Update coreboot timestamp table with CSE timestamps */
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if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
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cse_get_telemetry_data();
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/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
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systemagent_early_init();
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/* Program SMBus base address and enable it */
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