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vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 

Update FSP headers for Tiger Lake platform generated based on FSP
version 3444. Previous version was 3425.

BUG=b:173160613
BRANCH=none
TEST=build and boot delbin

Cq-Depend:chrome-internal:3403586, chrome-internal:3403392
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-11-12 20:19:04 -08:00 committed by Nick Vaccaro
parent c66e1c2a31
commit 34c5905614
2 changed files with 6 additions and 6 deletions
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6
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
View File

@ -2498,7 +2498,7 @@ typedef struct {
/** Offset 0x091C - Reserved
**/
UINT8 Reserved45[36];
UINT8 Reserved45[44];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@ -2517,11 +2517,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
/** Offset 0x0940
/** Offset 0x0948
**/
UINT8 UnusedUpdSpace27[6];
/** Offset 0x0946
/** Offset 0x094E
**/
UINT16 UpdTerminator;
} FSPM_UPD;

6
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
View File

@ -1058,10 +1058,10 @@ typedef struct {
UINT16 ITbtDmaLtr[2];
/** Offset 0x04E2 - Enable/Disable CrashLog
Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
Deprecated. Move to PreMem
$EN_DIS
**/
UINT8 CpuCrashLogEnable;
UINT8 DeprecatedCpuCrashLogEnable;
/** Offset 0x04E3 - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
@ -2838,7 +2838,7 @@ typedef struct {
/** Offset 0x0B95 - Configuration for boot TDP selection
Deprecated. Move to premem.
**/
UINT8 ConfigTdpLevel;
UINT8 DeprecatedConfigTdpLevel;
/** Offset 0x0B96 - Max P-State Ratio
Max P-State Ratio, Valid Range 0 to 0x7F