device/pci_ops: Reuse romstage PCI config for ramstage
By changing the signatures we do not need to define PCI config accessors separately for ramstage. Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
parent
74aa99a543
commit
34cf5619f9
|
@ -14,65 +14,17 @@
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
#include <device/pci.h>
|
#include <device/pci.h>
|
||||||
#include <device/pci_ops.h>
|
#include <device/pci_ops.h>
|
||||||
|
#include <arch/pci_io_cfg.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Functions for accessing PCI configuration space with type 1 accesses
|
* Functions for accessing PCI configuration space with type 1 accesses
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if !CONFIG(PCI_IO_CFG_EXT)
|
|
||||||
#define CONF_CMD(dev, reg) (0x80000000 | ((dev)->bus->secondary << 16) | \
|
|
||||||
((dev)->path.pci.devfn << 8) | (reg & ~3))
|
|
||||||
#else
|
|
||||||
#define CONF_CMD(dev, reg) (0x80000000 | ((dev)->bus->secondary << 16) | \
|
|
||||||
((dev)->path.pci.devfn << 8) | ((reg & 0xff) & ~3) |\
|
|
||||||
((reg & 0xf00)<<16))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static uint8_t pci_conf1_read_config8(const struct device *dev, uint16_t reg)
|
|
||||||
{
|
|
||||||
outl(CONF_CMD(dev, reg), 0xCF8);
|
|
||||||
return inb(0xCFC + (reg & 3));
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint16_t pci_conf1_read_config16(const struct device *dev, uint16_t reg)
|
|
||||||
{
|
|
||||||
outl(CONF_CMD(dev, reg), 0xCF8);
|
|
||||||
return inw(0xCFC + (reg & 2));
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t pci_conf1_read_config32(const struct device *dev, uint16_t reg)
|
|
||||||
{
|
|
||||||
outl(CONF_CMD(dev, reg), 0xCF8);
|
|
||||||
return inl(0xCFC);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pci_conf1_write_config8(const struct device *dev, uint16_t reg,
|
|
||||||
uint8_t value)
|
|
||||||
{
|
|
||||||
outl(CONF_CMD(dev, reg), 0xCF8);
|
|
||||||
outb(value, 0xCFC + (reg & 3));
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pci_conf1_write_config16(const struct device *dev, uint16_t reg,
|
|
||||||
uint16_t value)
|
|
||||||
{
|
|
||||||
outl(CONF_CMD(dev, reg), 0xCF8);
|
|
||||||
outw(value, 0xCFC + (reg & 2));
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pci_conf1_write_config32(const struct device *dev, uint16_t reg,
|
|
||||||
uint32_t value)
|
|
||||||
{
|
|
||||||
outl(CONF_CMD(dev, reg), 0xCF8);
|
|
||||||
outl(value, 0xCFC);
|
|
||||||
}
|
|
||||||
|
|
||||||
#undef CONF_CMD
|
|
||||||
|
|
||||||
const struct pci_bus_operations pci_cf8_conf1 = {
|
const struct pci_bus_operations pci_cf8_conf1 = {
|
||||||
.read8 = pci_conf1_read_config8,
|
.read8 = pci_io_read_config8,
|
||||||
.read16 = pci_conf1_read_config16,
|
.read16 = pci_io_read_config16,
|
||||||
.read32 = pci_conf1_read_config32,
|
.read32 = pci_io_read_config32,
|
||||||
.write8 = pci_conf1_write_config8,
|
.write8 = pci_io_write_config8,
|
||||||
.write16 = pci_conf1_write_config16,
|
.write16 = pci_io_write_config16,
|
||||||
.write32 = pci_conf1_write_config32,
|
.write32 = pci_io_write_config32,
|
||||||
};
|
};
|
||||||
|
|
|
@ -14,6 +14,7 @@
|
||||||
#include <device/mmio.h>
|
#include <device/mmio.h>
|
||||||
#include <device/pci.h>
|
#include <device/pci.h>
|
||||||
#include <device/pci_ops.h>
|
#include <device/pci_ops.h>
|
||||||
|
#include <device/pci_mmio_cfg.h>
|
||||||
|
|
||||||
#if (CONFIG_MMCONF_BASE_ADDRESS == 0)
|
#if (CONFIG_MMCONF_BASE_ADDRESS == 0)
|
||||||
#error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!"
|
#error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!"
|
||||||
|
@ -23,52 +24,13 @@
|
||||||
* Functions for accessing PCI configuration space with mmconf accesses
|
* Functions for accessing PCI configuration space with mmconf accesses
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define PCI_MMIO_ADDR(dev, reg, mask) \
|
|
||||||
((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\
|
|
||||||
(((dev)->bus->secondary & 0xFFF) << 20) |\
|
|
||||||
(((dev)->path.pci.devfn & 0xFF) << 12) |\
|
|
||||||
((reg) & 0xFFF)) & ~mask))
|
|
||||||
|
|
||||||
static uint8_t pci_mmconf_read_config8(const struct device *dev, uint16_t reg)
|
|
||||||
{
|
|
||||||
return read8(PCI_MMIO_ADDR(dev, reg, 0));
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint16_t pci_mmconf_read_config16(const struct device *dev, uint16_t reg)
|
|
||||||
{
|
|
||||||
return read16(PCI_MMIO_ADDR(dev, reg, 1));
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t pci_mmconf_read_config32(const struct device *dev, uint16_t reg)
|
|
||||||
{
|
|
||||||
return read32(PCI_MMIO_ADDR(dev, reg, 3));
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pci_mmconf_write_config8(const struct device *dev, uint16_t reg,
|
|
||||||
uint8_t value)
|
|
||||||
{
|
|
||||||
write8(PCI_MMIO_ADDR(dev, reg, 0), value);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pci_mmconf_write_config16(const struct device *dev, uint16_t reg,
|
|
||||||
uint16_t value)
|
|
||||||
{
|
|
||||||
write16(PCI_MMIO_ADDR(dev, reg, 1), value);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pci_mmconf_write_config32(const struct device *dev, uint16_t reg,
|
|
||||||
uint32_t value)
|
|
||||||
{
|
|
||||||
write32(PCI_MMIO_ADDR(dev, reg, 3), value);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct pci_bus_operations pci_ops_mmconf = {
|
static const struct pci_bus_operations pci_ops_mmconf = {
|
||||||
.read8 = pci_mmconf_read_config8,
|
.read8 = pci_mmio_read_config8,
|
||||||
.read16 = pci_mmconf_read_config16,
|
.read16 = pci_mmio_read_config16,
|
||||||
.read32 = pci_mmconf_read_config32,
|
.read32 = pci_mmio_read_config32,
|
||||||
.write8 = pci_mmconf_write_config8,
|
.write8 = pci_mmio_write_config8,
|
||||||
.write16 = pci_mmconf_write_config16,
|
.write16 = pci_mmio_write_config16,
|
||||||
.write32 = pci_mmconf_write_config32,
|
.write32 = pci_mmio_write_config32,
|
||||||
};
|
};
|
||||||
|
|
||||||
const struct pci_bus_operations *pci_bus_default_ops(void)
|
const struct pci_bus_operations *pci_bus_default_ops(void)
|
||||||
|
|
|
@ -35,14 +35,17 @@ struct pci_operations {
|
||||||
|
|
||||||
/* Common pci bus operations */
|
/* Common pci bus operations */
|
||||||
struct pci_bus_operations {
|
struct pci_bus_operations {
|
||||||
uint8_t (*read8)(const struct device *dev, uint16_t reg);
|
uint8_t (*read8)(pci_devfn_t dev, uint16_t reg);
|
||||||
uint16_t (*read16)(const struct device *dev, uint16_t reg);
|
uint16_t (*read16)(pci_devfn_t dev, uint16_t reg);
|
||||||
uint32_t (*read32)(const struct device *dev, uint16_t reg);
|
uint32_t (*read32)(pci_devfn_t dev, uint16_t reg);
|
||||||
void (*write8)(const struct device *dev, uint16_t reg, uint8_t val);
|
void (*write8)(pci_devfn_t dev, uint16_t reg, uint8_t val);
|
||||||
void (*write16)(const struct device *dev, uint16_t reg, uint16_t val);
|
void (*write16)(pci_devfn_t dev, uint16_t reg, uint16_t val);
|
||||||
void (*write32)(const struct device *dev, uint16_t reg, uint32_t val);
|
void (*write32)(pci_devfn_t dev, uint16_t reg, uint32_t val);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
// FIXME: Needs complete pci_bus_operations
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
|
||||||
struct pci_driver {
|
struct pci_driver {
|
||||||
const struct device_operations *ops;
|
const struct device_operations *ops;
|
||||||
unsigned short vendor;
|
unsigned short vendor;
|
||||||
|
|
|
@ -48,52 +48,58 @@ static __always_inline const struct pci_bus_operations *pci_bus_ops(void)
|
||||||
|
|
||||||
void __noreturn pcidev_die(void);
|
void __noreturn pcidev_die(void);
|
||||||
|
|
||||||
static __always_inline void pcidev_assert(const struct device *dev)
|
static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev)
|
||||||
|
{
|
||||||
|
return (dev->path.pci.devfn << 12) | (dev->bus->secondary << 20);
|
||||||
|
}
|
||||||
|
|
||||||
|
static __always_inline pci_devfn_t pcidev_assert(const struct device *dev)
|
||||||
{
|
{
|
||||||
if (!dev)
|
if (!dev)
|
||||||
pcidev_die();
|
pcidev_die();
|
||||||
|
return pcidev_bdf(dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
static __always_inline
|
static __always_inline
|
||||||
u8 pci_read_config8(const struct device *dev, u16 reg)
|
u8 pci_read_config8(const struct device *dev, u16 reg)
|
||||||
{
|
{
|
||||||
pcidev_assert(dev);
|
pci_devfn_t bdf = PCI_BDF(dev);
|
||||||
return pci_bus_ops()->read8(dev, reg);
|
return pci_bus_ops()->read8(bdf, reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
static __always_inline
|
static __always_inline
|
||||||
u16 pci_read_config16(const struct device *dev, u16 reg)
|
u16 pci_read_config16(const struct device *dev, u16 reg)
|
||||||
{
|
{
|
||||||
pcidev_assert(dev);
|
pci_devfn_t bdf = PCI_BDF(dev);
|
||||||
return pci_bus_ops()->read16(dev, reg);
|
return pci_bus_ops()->read16(bdf, reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
static __always_inline
|
static __always_inline
|
||||||
u32 pci_read_config32(const struct device *dev, u16 reg)
|
u32 pci_read_config32(const struct device *dev, u16 reg)
|
||||||
{
|
{
|
||||||
pcidev_assert(dev);
|
pci_devfn_t bdf = PCI_BDF(dev);
|
||||||
return pci_bus_ops()->read32(dev, reg);
|
return pci_bus_ops()->read32(bdf, reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
static __always_inline
|
static __always_inline
|
||||||
void pci_write_config8(const struct device *dev, u16 reg, u8 val)
|
void pci_write_config8(const struct device *dev, u16 reg, u8 val)
|
||||||
{
|
{
|
||||||
pcidev_assert(dev);
|
pci_devfn_t bdf = PCI_BDF(dev);
|
||||||
pci_bus_ops()->write8(dev, reg, val);
|
pci_bus_ops()->write8(bdf, reg, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
static __always_inline
|
static __always_inline
|
||||||
void pci_write_config16(const struct device *dev, u16 reg, u16 val)
|
void pci_write_config16(const struct device *dev, u16 reg, u16 val)
|
||||||
{
|
{
|
||||||
pcidev_assert(dev);
|
pci_devfn_t bdf = PCI_BDF(dev);
|
||||||
pci_bus_ops()->write16(dev, reg, val);
|
pci_bus_ops()->write16(bdf, reg, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
static __always_inline
|
static __always_inline
|
||||||
void pci_write_config32(const struct device *dev, u16 reg, u32 val)
|
void pci_write_config32(const struct device *dev, u16 reg, u32 val)
|
||||||
{
|
{
|
||||||
pcidev_assert(dev);
|
pci_devfn_t bdf = PCI_BDF(dev);
|
||||||
pci_bus_ops()->write32(dev, reg, val);
|
pci_bus_ops()->write32(bdf, reg, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -25,4 +25,15 @@ typedef u32 pci_devfn_t;
|
||||||
|
|
||||||
#define PCI_DEV_INVALID (0xffffffffU)
|
#define PCI_DEV_INVALID (0xffffffffU)
|
||||||
|
|
||||||
|
#if 1
|
||||||
|
/* FIXME: For most of the time in ramstage, we get valid device pointer
|
||||||
|
* from calling the driver entry points. The assert should only be used
|
||||||
|
* with searches like pcidev_behind(), and only if caller does not make
|
||||||
|
* the check themselves.
|
||||||
|
*/
|
||||||
|
#define PCI_BDF(dev) pcidev_assert((dev))
|
||||||
|
#else
|
||||||
|
#define PCI_BDF(dev) pcidev_bdf((dev))
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* DEVICE_PCI_TYPE_H */
|
#endif /* DEVICE_PCI_TYPE_H */
|
||||||
|
|
Loading…
Reference in New Issue