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mb/google/volteer: add touchscreen entry to Volteer 

BUG=b:149588766
TEST=ELAN and Goodix touchscreen works.

Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I1c3e75eb03a8ab434ee58bf36a155f2255612083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Alex Levin 2020-04-20 21:55:24 -07:00 committed by Furquan Shaikh
parent d6f7ec5f44
commit 34d9e68ff9
3 changed files with 35 additions and 4 deletions
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1
src/mainboard/google/volteer/Kconfig
View File

@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
select BOARD_ROMSIZE_KB_32768 select BOARD_ROMSIZE_KB_32768
select DRIVERS_GENERIC_MAX98357A select DRIVERS_GENERIC_MAX98357A
select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_BOARDID

32
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -251,7 +251,37 @@ chip soc/intel/tigerlake
device i2c 1a on end device i2c 1a on end
end end
end # I2C #0 0xA0E8 end # I2C #0 0xA0E8
device pci 15.1 on end # I2C1 0xA0E9 device pci 15.1 on
chip drivers/i2c/hid
register "generic.hid" = ""GDIX0000""
register "generic.desc" = ""Goodix Touchscreen""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
register "generic.reset_delay_ms" = "120"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 14 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""ELAN90FC""
register "generic.desc" = ""ELAN Touchscreen""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
register "generic.reset_delay_ms" = "20"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
end # I2C1 0xA0E9
device pci 15.2 on device pci 15.2 on
chip drivers/i2c/sx9310 chip drivers/i2c/sx9310
register "desc" = ""SAR0 Proximity Sensor"" register "desc" = ""SAR0 Proximity Sensor""

6
src/mainboard/google/volteer/variants/baseboard/gpio.c
View File

@ -23,7 +23,7 @@ static const struct pad_config gpio_table[] = {
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
PAD_CFG_GPO(GPP_A7, 1, DEEP), PAD_CFG_GPO(GPP_A7, 1, DEEP),
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
PAD_CFG_GPO(GPP_A8, 1, DEEP), PAD_CFG_GPO(GPP_A8, 0, DEEP),
/* A9 : I2S2_TXD ==> EC_IN_RW_OD */ /* A9 : I2S2_TXD ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_A9, NONE, DEEP), PAD_CFG_GPI(GPP_A9, NONE, DEEP),
/* A10 : I2S2_RXD ==> EN_SPKR_PA */ /* A10 : I2S2_RXD ==> EN_SPKR_PA */
@ -125,7 +125,7 @@ static const struct pad_config gpio_table[] = {
/* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
/* C10 : UART0_RTS# ==> USI_RST_L */ /* C10 : UART0_RTS# ==> USI_RST_L */
PAD_CFG_GPO(GPP_C10, 1, DEEP), PAD_CFG_GPO(GPP_C10, 0, DEEP),
/* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */
PAD_CFG_GPI(GPP_C11, NONE, DEEP), PAD_CFG_GPI(GPP_C11, NONE, DEEP),
/* C12 : UART1_RXD ==> MEM_STRAP_0 */ /* C12 : UART1_RXD ==> MEM_STRAP_0 */
@ -210,7 +210,7 @@ static const struct pad_config gpio_table[] = {
/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
PAD_NC(GPP_E6, NONE), PAD_NC(GPP_E6, NONE),
/* E7 : CPU_GP1 ==> USI_INT */ /* E7 : CPU_GP1 ==> USI_INT */
PAD_CFG_GPI(GPP_E7, NONE, DEEP), PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
/* E8 : SPI1_CS1# ==> SLP_S0IX */ /* E8 : SPI1_CS1# ==> SLP_S0IX */
PAD_CFG_GPO(GPP_E8, 0, DEEP), PAD_CFG_GPO(GPP_E8, 0, DEEP),
/* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */