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soc/intel/tigerlake: Replace spaces with tabs 

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sean Rhodes 2022-05-21 10:41:32 +01:00 committed by Felix Held
parent 121ff62768
commit 34e3fac130
1 changed files with 5 additions and 5 deletions
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10
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
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@ -6,19 +6,19 @@
* port of the USB4/TBT topology. * port of the USB4/TBT topology.
*/ */
/* Number of microseconds to wait after a conventional reset */ /* Number of microseconds to wait after a conventional reset */
#define FW_RESET_TIME 50000 #define FW_RESET_TIME 50000
/* Number of microseconds to wait after data link layer active report */ /* Number of microseconds to wait after data link layer active report */
#define FW_DL_UP_TIME 1 #define FW_DL_UP_TIME 1
/* Number of microseconds to wait after a function level reset */ /* Number of microseconds to wait after a function level reset */
#define FW_FLR_RESET_TIME 1 #define FW_FLR_RESET_TIME 1
/* Number of microseconds to wait from D3 hot to D0 transition */ /* Number of microseconds to wait from D3 hot to D0 transition */
#define FW_D3HOT_TO_D0_TIME 50000 #define FW_D3HOT_TO_D0_TIME 50000
/* Number of microseconds to wait after setting the VF enable bit */ /* Number of microseconds to wait after setting the VF enable bit */
#define FW_VF_ENABLE_TIME 1 #define FW_VF_ENABLE_TIME 1
OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800)
Field (PXCS, AnyAcc, NoLock, Preserve) Field (PXCS, AnyAcc, NoLock, Preserve)