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drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs 

This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_"  prefix.

1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
          USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
          USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
          USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.

For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.

Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

Additionally, fixed SoC configs inclusion order alphabetically. 

BUG=b:211954778
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Subrata Banik 2022-02-10 12:38:02 +05:30 committed by Felix Held
parent 03c0853f4d
commit 34f26b2989
16 changed files with 131 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
src/drivers/intel/fsp2_0/Kconfig
View File

@ -310,7 +310,7 @@ config FSPS_USE_MULTI_PHASE_INIT
SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and
execute FspMultiPhaseSiInit() API.
config SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM
config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
bool
help
The FSP API is used to notify the FSP about different phases in the boot process.
@ -318,12 +318,28 @@ config SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM
- Post PCI enumeration
- Ready to Boot
- End of Firmware
Select this on a platform where you want to skip calling FSP Notify
`Post PCI enumeration` API. Instead use coreboot native implementations
This option allows FSP to execute Notify Phase API (Post PCI enumeration).
SoC users can override this config to use coreboot native implementations
to perform the required lock down and chipset register configuration prior
to executing any 3rd-party code during PCI enumeration (i.e. Option ROM).
coreboot native implementation to skip FSP Notify Phase (Post PCI enumeration)
is still WIP.
config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
bool
help
The FSP API is used to notify the FSP about different phases in the boot process.
The current FSP specification supports three notify phases:
- Post PCI enumeration
- Ready to Boot
- End of Firmware
This option allows FSP to execute Notify Phase API (Ready to Boot).
SoC users can override this config to use coreboot native implementations
to perform the required lock down and chipset register configuration prior
boot to payload.
config SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
bool
help
The FSP API is used to notify the FSP about different phases in the boot process.
@ -331,20 +347,9 @@ config SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
- Post PCI enumeration
- Ready to Boot
- End of Firmware
Select this on a platform where you want to skip calling FSP Notify `Ready to Boot`
API. Instead use coreboot native implementations to perform the required lock down
and chipset register configuration prior boot to payload.
config SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
bool
help
The FSP API is used to notify the FSP about different phases in the boot process.
The current FSP specification supports three notify phases:
- Post PCI enumeration
- Ready to Boot
- End of Firmware
Select this on a platform where you want to skip calling FSP Notify `End of Firmware`
API. Instead use coreboot native implementations to perform the required lock down
and chipset register configuration prior boot to payload.
This option allows FSP to execute Notify Phase API (End of Firmware).
SoC users can override this config to use coreboot native implementations
to perform the required lock down and chipset register configuration prior
boot to payload.
endif

6
src/drivers/intel/fsp2_0/notify.c
View File

@ -20,7 +20,7 @@ struct fsp_notify_phase_data {
static const struct fsp_notify_phase_data notify_data[] = {
{
.notify_phase = AFTER_PCI_ENUM,
.skip = CONFIG(SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM),
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
.post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE,
.timestamp_before = TS_FSP_BEFORE_ENUMERATE,
@ -28,7 +28,7 @@ static const struct fsp_notify_phase_data notify_data[] = {
},
{
.notify_phase = READY_TO_BOOT,
.skip = CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT),
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
.post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE,
.timestamp_before = TS_FSP_BEFORE_FINALIZE,
@ -36,7 +36,7 @@ static const struct fsp_notify_phase_data notify_data[] = {
},
{
.notify_phase = END_OF_FIRMWARE,
.skip = CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
.post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
.timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE,

3
src/soc/amd/cezanne/Kconfig
View File

@ -72,6 +72,9 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_FSP_PCI
select SSE2
select UDK_2017_BINDING
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI

33
src/soc/amd/picasso/Kconfig
View File

@ -9,23 +9,30 @@ if SOC_AMD_PICASSO
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_SOC_NVS
select ADD_FSP_BINARIES if USE_AMD_BLOBS
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_X86
select RESET_VECTOR_IN_RAM
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI
select ACPI_SOC_NVS
select ADD_FSP_BINARIES if USE_AMD_BLOBS
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select DRIVERS_I2C_DESIGNWARE
select DRIVERS_USB_PCI_XHCI
select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA
select GENERIC_GPIO_LIB
select IDT_IN_EVERY_STAGE
select HAVE_ACPI_TABLES
select HAVE_CF9_RESET
select HAVE_EM100_SUPPORT
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
select PROVIDES_ROM_SHARING
select RESET_VECTOR_IN_RAM
select RTC
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACP_GEN1
select SOC_AMD_COMMON_BLOCK_ACPI
@ -61,17 +68,13 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_UCODE
select SOC_AMD_COMMON_FSP_DMI_TABLES
select PROVIDES_ROM_SHARING
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select PARALLEL_MP_AP_WORK
select HAVE_SMI_HANDLER
select SSE2
select RTC
select PLATFORM_USES_FSP2_0
select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA
select UDK_2017_BINDING
select HAVE_CF9_RESET
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI
config ARCH_ALL_STAGES_X86
default n

3
src/soc/amd/sabrina/Kconfig
View File

@ -76,6 +76,9 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
select SSE2
select UDK_2017_BINDING
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI

5
src/soc/intel/alderlake/Kconfig
View File

@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_INTEL_TME
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DISPLAY_FSP_VERSION_INFO
select DRIVERS_USB_ACPI
select FSP_COMPRESS_FSP_S_LZ4
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
@ -106,7 +107,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_202005_BINDING
select DISPLAY_FSP_VERSION_INFO
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
bool

31
src/soc/intel/apollolake/Kconfig
View File

@ -41,18 +41,27 @@ config CPU_SPECIFIC_OPTIONS
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select FSP_STATUS_GLOBAL_RESET_REQUIRED_5
select GENERIC_GPIO_LIB
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select HAVE_ASAN_IN_ROMSTAGE
select HAVE_CF9_RESET_PREPARE
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE
select HAVE_SMI_HANDLER
select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select INTEL_GMA_SWSMISCI
select MRC_SETTINGS_PROTECT
select MRC_SETTINGS_VARIABLE_DATA
select NO_XIP_EARLY_STAGES
select NO_PM_ACPI_TIMER
select NO_UART_ON_SUPERIO
select NO_XIP_EARLY_STAGES
select PARALLEL_MP_AP_WORK
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select PCIEXP_CLK_PM
select PCIEXP_L1_SUB_STATE
select PLATFORM_USES_FSP2_0
select PMC_INVALID_READ_AFTER_WRITE
select PMC_GLOBAL_RESET_ENABLE_LOCK
select REG_SCRIPT
@ -97,22 +106,16 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_NO_BOOTGUARD_MSR
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select PLATFORM_USES_FSP2_0
select UDELAY_TSC
select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE
select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE
select SOC_INTEL_COMMON_RESET
select HAVE_CF9_RESET_PREPARE
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
select NO_UART_ON_SUPERIO
select INTEL_GMA_ACPI
select INTEL_GMA_SWSMISCI
select HAVE_ASAN_IN_ROMSTAGE
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
# This SoC does not map SPI flash like many previous SoC. Therefore we
# provide a custom media driver that facilitates mapping
select X86_CUSTOM_BOOTMEDIA

3
src/soc/intel/cannonlake/Kconfig
View File

@ -110,6 +110,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config MAX_CPUS
int

24
src/soc/intel/denverton_ns/Kconfig
View File

@ -15,17 +15,20 @@ config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DEBUG_GPIO
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select PLATFORM_USES_FSP2_0
select FSP_M_XIP
select FSP_T_XIP if FSP_CAR
select HAVE_INTEL_FSP_REPO
select HAVE_SMI_HANDLER
select CACHE_MRC_SETTINGS
select PCR_COMMON_IOSF_1_0
select SUPPORT_CPU_UCODE_IN_CBFS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select PCR_COMMON_IOSF_1_0
select PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_ACPI
@ -35,16 +38,15 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SUPPORT_CPU_UCODE_IN_CBFS
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS
select FSP_T_XIP if FSP_CAR
select FSP_M_XIP
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000

9
src/soc/intel/elkhartlake/Kconfig
View File

@ -14,15 +14,16 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DISPLAY_FSP_VERSION_INFO
select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM
select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select MP_SERVICES_PPI_V1
@ -46,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
@ -61,8 +63,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_202005_BINDING
select DISPLAY_FSP_VERSION_INFO
select HAVE_INTEL_FSP_REPO
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config MAX_CPUS
int

5
src/soc/intel/icelake/Kconfig
View File

@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS
select SET_IA32_FC_LOCK_BIT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DISPLAY_FSP_VERSION_INFO
select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB
@ -60,7 +61,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
config DISABLE_HECI1_AT_PRE_BOOT

7
src/soc/intel/jasperlake/Kconfig
View File

@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select COS_MAPPED_TO_MSB
select DISPLAY_FSP_VERSION_INFO_2
select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
@ -22,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
@ -63,8 +65,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_202005_BINDING
select DISPLAY_FSP_VERSION_INFO_2
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config DCACHE_RAM_BASE
default 0xfef00000

5
src/soc/intel/quark/Kconfig
View File

@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select NO_ECAM_MMCONF_SUPPORT
select NO_SMM
select REG_SCRIPT
select PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON
@ -21,8 +22,10 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNCOMPRESSED_RAMSTAGE
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select USE_MARCH_586
select NO_SMM
#####
# Debug serial output

3
src/soc/intel/skylake/Kconfig
View File

@ -86,6 +86,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config MAX_HECI_DEVICES
int

5
src/soc/intel/tigerlake/Kconfig
View File

@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_INTEL_TME
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DISPLAY_FSP_VERSION_INFO
select DRIVERS_USB_ACPI
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_COMPRESS_FSP_S_LZ4
@ -84,7 +85,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config MAX_CPUS
int

31
src/soc/intel/xeon_sp/Kconfig
View File

@ -26,18 +26,26 @@ if XEON_SP_COMMON_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES
select CPU_INTEL_COMMON
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_CAR
select FSP_M_XIP
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select FSP_T_XIP
select FSP_M_XIP
select POSTCAR_STAGE
select HAVE_SMI_HANDLER
select INTEL_CAR_NEM # For postcar only now
select INTEL_DESCRIPTOR_MODE_CAPABLE
select NO_FSP_TEMP_RAM_EXIT
select PARALLEL_MP_AP_WORK
select PMC_GLOBAL_RESET_ENABLE_LOCK
select INTEL_DESCRIPTOR_MODE_CAPABLE
select POSTCAR_STAGE
select REG_SCRIPT
select SMM_TSEG
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
@ -47,18 +55,13 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_SERVER
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_CAR
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SMM_TSEG
select HAVE_SMI_HANDLER
select REG_SCRIPT
select NO_FSP_TEMP_RAM_EXIT
select INTEL_CAR_NEM # For postcar only now
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config MAINBOARD_USES_FSP2_0
bool