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mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP 

Add support for Alder lake N LP5 RVP with board ID 0x7.
Since SPD index 7 is unused earlier, ADL-N will use it.

Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Krishna Prasad Bhat 2021-12-17 16:08:04 +05:30 committed by Felix Held
parent 8fac662f30
commit 351d3a1967
5 changed files with 100 additions and 1 deletions
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2
src/mainboard/intel/adlrvp/include/baseboard/variants.h
View File

@ -24,6 +24,8 @@ enum adl_boardid {
/* ADL-M LP4 and LP5 RVPs */
ADL_M_LP4 = 0x1,
ADL_M_LP5 = 0x2,
/* ADL-N LP5 RVP */
ADL_N_LP5 = 0x7,
};
/* The next set of functions return the gpio table and fill in the number of

64
src/mainboard/intel/adlrvp/memory.c
View File

@ -290,6 +290,68 @@ static const struct mb_cfg adlm_lp5_mem_config = {
},
};
static const struct mb_cfg adln_lp5_mem_config = {
.type = MEM_TYPE_LP5X,
/* DQ byte map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
},
.ddr1 = {
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
},
.ddr2 = {
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
},
.ddr3 = {
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
},
.ddr4 = {
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
},
.ddr5 = {
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
},
.ddr6 = {
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
},
.ddr7 = {
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
},
},
/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
},
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_ULT_ULX,
.LpDdrDqDqsReTraining = 1,
.lp5x_config = {
.ccc_config = 0xff,
},
};
const struct mb_cfg *variant_memory_params(void)
{
int board_id = get_board_id();
@ -311,6 +373,8 @@ const struct mb_cfg *variant_memory_params(void)
return &adlm_lp4_mem_config;
case ADL_M_LP5:
return &adlm_lp5_mem_config;
case ADL_N_LP5:
return &adln_lp5_mem_config;
default:
die("unsupported board id : 0x%x\n", board_id);
}

1
src/mainboard/intel/adlrvp/romstage_fsp_params.c
View File

@ -80,6 +80,7 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
case ADL_P_LP5_2:
case ADL_M_LP4:
case ADL_M_LP5:
case ADL_N_LP5:
memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated);
break;
default:

2
src/mainboard/intel/adlrvp/spd/Makefile.inc
View File

@ -7,4 +7,4 @@ SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
SPD_SOURCES += adlrvp_ddr5_mr # 0b006
SPD_SOURCES += adlrvp_lp5 # 0b007
SPD_SOURCES += adlrvp_n_lp5 # 0b007

32
src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex Normal file
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@ -0,0 +1,32 @@
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