src: Use include <console/console.h> when appropriate

Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian

src/arch/riscv/sbi.c

@@ -20,7 +20,6 @@
 #include <sbi.h>
 #include <vm.h>
 #include <console/uart.h>
-#include <console/console.h>
 #include <commonlib/helpers.h>
 
 static uintptr_t send_ipi(uintptr_t *pmask, intptr_t type)

src/device/oprom/include/x86emu/x86emu.h

@@ -42,7 +42,6 @@
 #define __X86EMU_X86EMU_H
 
 #include <stddef.h>
-#include <console/console.h>
 #if CONFIG(X86EMU_DEBUG)
 #define DEBUG
 #endif

src/drivers/amd/agesa/state_machine.c

@@ -16,17 +16,15 @@
 
 #include <stdint.h>
 #include <string.h>
-
 #include <arch/acpi.h>
 #include <arch/cpu.h>
 #include <bootstate.h>
 #include <cbfs.h>
-
+#include <console/console.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <amdlib.h>
-
 #include <AMD.h>
 
 #if CONFIG(CPU_AMD_AGESA_OPENSOURCE)

src/drivers/generic/gpio_keys/gpio_keys.c

@@ -15,7 +15,6 @@
 
 #include <arch/acpi_device.h>
 #include <arch/acpigen.h>
-#include <console/console.h>
 #include <device/device.h>
 #include <device/path.h>
 #include <string.h>

src/drivers/generic/gpio_regulator/gpio_regulator.c

@@ -15,7 +15,6 @@
 
 #include <arch/acpi_device.h>
 #include <arch/acpigen.h>
-#include <console/console.h>
 #include <device/device.h>
 #include <device/path.h>
 #include <string.h>

src/drivers/intel/fsp1_0/fsp_util.h

@@ -17,6 +17,8 @@
 #define FSP_UTIL_H
 
 #include <chipset_fsp_util.h>
+#include <console/console.h>
+
 #include "fsp_values.h"
 
 #if CONFIG(ENABLE_MRC_CACHE)

src/drivers/intel/gma/int15.c

@@ -16,6 +16,8 @@
 
 #include <x86emu/x86emu.h>
 #include <arch/interrupt.h>
+#include <console/console.h>
+
 #include "int15.h"
 
 static int active_lfp, pfit, display, panel_type;

src/include/device/azalia_device.h

@@ -17,11 +17,9 @@
 #define DEVICE_AZALIA_H
 
 #include <types.h>
-#include <console/console.h>
 #include <arch/acpi.h>
 #include <device/mmio.h>
 #include <arch/interrupt.h>
-
 #include <device/device.h>
 
 void azalia_audio_init(struct device *dev);

src/lib/cbfs.c

@@ -15,6 +15,7 @@
  */
 
 #include <assert.h>
+#include <console/console.h>
 #include <string.h>
 #include <stdlib.h>
 #include <boot_device.h>

src/lib/cbmem_console.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
 #include <console/cbmem_console.h>
 #include <console/uart.h>
 #include <cbmem.h>

src/lib/fit.c

@@ -16,6 +16,7 @@
  */
 
 #include <assert.h>
+#include <console/console.h>
 #include <endian.h>
 #include <stdint.h>
 #include <bootmem.h>

src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c

@@ -15,6 +15,7 @@
  */
 
 #include <AGESA.h>
+#include <console/console.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <device/azalia.h>
 #include <FchPlatform.h>

src/mainboard/amd/lamar/BiosCallOuts.c

@@ -14,6 +14,7 @@
  */
 
 #include <AGESA.h>
+#include <console/console.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <FchPlatform.h>
 #include <stdlib.h>

src/mainboard/amd/olivehillplus/BiosCallOuts.c

@@ -14,6 +14,7 @@
  */
 
 #include <AGESA.h>
+#include <console/console.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <FchPlatform.h>
 #include <stdlib.h>

src/mainboard/amd/thatcher/romstage.c

@@ -16,10 +16,10 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <console/console.h>
 #include <device/pci_ops.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
-
 #include <superio/smsc/lpc47n217/lpc47n217.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)

src/mainboard/asus/am1i-a/BiosCallOuts.c

@@ -17,6 +17,7 @@
 
 #include <device/azalia.h>
 #include <AGESA.h>
+#include <console/console.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <FchPlatform.h>

src/mainboard/asus/f2a85-m/romstage.c

@@ -15,15 +15,14 @@
  */
 
 #include <arch/io.h>
+#include <console/console.h>
 #include <device/pnp_type.h>
 #include <device/pci_ops.h>
-
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/common/amd_defs.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 #include <southbridge/amd/agesa/hudson/smbus.h>
 #include <stdint.h>
-
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8728f/it8728f.h>
 #include <superio/nuvoton/common/nuvoton.h>

src/mainboard/asus/m4a785-m/acpi_tables.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
 #include <device/pci.h>

src/mainboard/cubietech/cubieboard/bootblock.c

@@ -22,7 +22,6 @@
 #include <device/mmio.h>
 #include <bootblock_common.h>
 #include <console/uart.h>
-#include <console/console.h>
 #include <delay.h>
 #include <cpu/allwinner/a10/gpio.h>
 #include <cpu/allwinner/a10/clock.h>

src/mainboard/google/beltino/smihandler.c

@@ -15,7 +15,6 @@
  */
 
 #include <arch/acpi.h>
-#include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <cpu/x86/smm.h>
 #include <northbridge/intel/haswell/haswell.h>
@@ -24,6 +23,7 @@
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <elog.h>
 #include <superio/ite/it8772f/it8772f.h>
+
 #include "onboard.h"
 
 void mainboard_smi_sleep(u8 slp_typ)

src/mainboard/google/daisy/chromeos.c

@@ -14,7 +14,6 @@
  */
 
 #include <boot/coreboot_tables.h>
-#include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <soc/cpu.h>

src/mainboard/google/dragonegg/romstage_fsp_params.c

@@ -15,7 +15,6 @@
 
 #include <assert.h>
 #include <baseboard/variants.h>
-#include <console/console.h>
 #include <soc/romstage.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)

src/mainboard/google/foster/chromeos.c

@@ -15,7 +15,6 @@
  */
 
 #include <boot/coreboot_tables.h>
-#include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <gpio.h>

src/mainboard/google/gru/bootblock.c

@@ -16,7 +16,6 @@
 
 #include <device/mmio.h>
 #include <bootblock_common.h>
-#include <console/console.h>
 #include <delay.h>
 #include <soc/grf.h>
 #include <gpio.h>

src/mainboard/google/octopus/variants/phaser/gpio.c

@@ -19,7 +19,6 @@
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
-#include <console/console.h>
 
 #define SKU_UNKNOWN            0xFFFFFFFF
 

src/mainboard/google/peach_pit/chromeos.c

@@ -15,7 +15,6 @@
 
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
-#include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <soc/cpu.h>

src/mainboard/google/poppy/variants/nami/smihandler.c

@@ -15,8 +15,8 @@
 
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
-#include <console/console.h>
 #include <delay.h>
+
 #include "gpio.h"
 
 #define TOUCH_DISABLE         GPP_C3

src/mainboard/google/urara/bootblock.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <console/console.h>
 #include <device/mmio.h>
 #include <stdint.h>
 #include <soc/clocks.h>

src/mainboard/intel/baskingridge/mainboard_smi.c

@@ -15,7 +15,6 @@
 
 #include <arch/acpi.h>
 #include <arch/io.h>
-#include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/lynxpoint/nvs.h>
 #include <southbridge/intel/lynxpoint/pch.h>

src/mainboard/intel/cannonlake_rvp/spd/spd_util.c

@@ -12,10 +12,11 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+
 #include <arch/byteorder.h>
-#include <console/console.h>
 #include <stdint.h>
 #include <string.h>
+
 #include "spd.h"
 
 void mainboard_fill_dq_map_ch0(void *dq_map_ptr)

src/mainboard/intel/icelake_rvp/romstage_fsp_params.c

@@ -14,12 +14,12 @@
  */
 
 #include <arch/byteorder.h>
-#include <console/console.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
-#include "spd/spd.h"
 #include <spd_bin.h>
 
+#include "spd/spd.h"
+
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 }

src/mainboard/intel/icelake_rvp/spd/spd_util.c

@@ -12,12 +12,13 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+
 #include <arch/byteorder.h>
 #include <arch/cpu.h>
-#include <console/console.h>
 #include <intelblocks/mp_init.h>
 #include <stdint.h>
 #include <string.h>
+
 #include "../board_id.h"
 #include "spd.h"
 

src/mainboard/intel/kblrvp/spd/spd_util.c

@@ -12,12 +12,13 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+
 #include <arch/byteorder.h>
-#include <console/console.h>
 #include <stdint.h>
 #include <string.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
+
 #include "../board_id.h"
 #include "spd.h"
 

src/mainboard/kontron/986lcd-m/mptable.c

@@ -15,7 +15,6 @@
 
 #include <device/device.h>
 #include <device/pci.h>
-#include <console/console.h>
 #include <arch/smp/mpspec.h>
 #include <arch/ioapic.h>
 #include <stdint.h>

src/mainboard/roda/rk886ex/mptable.c

@@ -16,7 +16,6 @@
 
 #include <device/device.h>
 #include <device/pci.h>
-#include <console/console.h>
 #include <arch/smp/mpspec.h>
 #include <arch/ioapic.h>
 #include <stdint.h>

src/mainboard/sifive/hifive-unleashed/mainboard.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
+#include <device/device.h>
 #include <soc/sdram.h>
 #include <symbols.h>
 

src/northbridge/amd/amdht/h3ncmn.h

@@ -19,8 +19,8 @@
 
 #include <inttypes.h>
 #include <device/pci.h>
-#include <console/console.h>
 #include <cpu/amd/msr.h>
+
 #include "comlib.h"
 #include "h3finit.h"
 #include "h3ffeat.h"

src/northbridge/amd/amdmct/mct/mct_d.h

@@ -23,11 +23,11 @@
 #define DQS_TRAIN_DEBUG 0
 
 #include <inttypes.h>
-#include "mct_d_gcc.h"
-#include <console/console.h>
 #include <northbridge/amd/amdfam10/debug.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 
+#include "mct_d_gcc.h"
+
 extern const u8 Table_DQSRcvEn_Offset[];
 extern const u32 TestPattern0_D[];
 extern const u32 TestPattern1_D[];

src/northbridge/amd/amdmct/mct/mctsrc.c

@@ -14,8 +14,10 @@
  * GNU General Public License for more details.
  */
 
+#include <console/console.h>
 #include <cpu/x86/cr.h>
 #include <cpu/amd/msr.h>
+
 #include "mct_d.h"
 
 /******************************************************************************

src/northbridge/via/vx900/vx900.h

@@ -28,7 +28,6 @@
 
 #include <device/pci_ops.h>
 #include <device/pci.h>
-#include <console/console.h>
 
 u32 vx900_get_tolm(void);
 void vx900_set_chrome9hd_fb_size(u32 size_mb);

src/soc/intel/apollolake/memmap.c

@@ -17,13 +17,15 @@
 
 #include <assert.h>
 #include <cbmem.h>
-#include "chip.h"
+#include <console/console.h>
 #include <device/pci.h>
 #include <fsp/memmap.h>
 #include <intelblocks/smm.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 
+#include "chip.h"
+
 void *cbmem_top(void)
 {
 	const struct device *dev;

src/soc/intel/fsp_baytrail/include/soc/i2c.h

@@ -16,7 +16,6 @@
 #ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__
 #define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__
 
-#include <console/console.h>
 #include <device/pci_def.h>
 #include <stdlib.h>
 

src/soc/intel/icelake/bootblock/pch.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>

src/soc/intel/icelake/chip.c

@@ -14,7 +14,6 @@
  */
 
 #include <chip.h>
-#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>

src/soc/intel/icelake/lpc.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <pc80/isa-dma.h>

src/soc/intel/icelake/systemagent.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <intelblocks/systemagent.h>

src/soc/mediatek/mt8183/auxadc.c

@@ -15,7 +15,6 @@
 
 #include <device/mmio.h>
 #include <assert.h>
-#include <console/console.h>
 #include <delay.h>
 #include <soc/addressmap.h>
 #include <soc/auxadc.h>

src/soc/qualcomm/ipq806x/uart.c

@@ -33,7 +33,6 @@
 
 #include <device/mmio.h>
 #include <boot/coreboot_tables.h>
-#include <console/console.h>
 #include <console/uart.h>
 #include <delay.h>
 #include <gpio.h>

src/soc/qualcomm/qcs405/clock.c

@@ -14,12 +14,10 @@
 
 #include <device/mmio.h>
 #include <types.h>
-#include <console/console.h>
 #include <delay.h>
 #include <timestamp.h>
 #include <commonlib/helpers.h>
 #include <string.h>
-
 #include <soc/clock.h>
 
 #define DIV(div) (div ? (2*div - 1) : 0)

src/soc/qualcomm/qcs405/gpio.c

@@ -15,10 +15,8 @@
 
 #include <device/mmio.h>
 #include <types.h>
-#include <console/console.h>
 #include <delay.h>
 #include <timestamp.h>
-
 #include <gpio.h>
 
 void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,

src/soc/qualcomm/sdm845/clock.c

@@ -15,7 +15,6 @@
 
 #include <device/mmio.h>
 #include <types.h>
-#include <console/console.h>
 #include <commonlib/helpers.h>
 #include <assert.h>
 #include <soc/clock.h>

src/southbridge/amd/amd8111/early_smbus.c

@@ -12,7 +12,9 @@
  */
 
 #include <arch/io.h>
+#include <console/console.h>
 #include <device/pci_ops.h>
+
 #include "amd8111_smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00

src/southbridge/amd/cimx/sb800/SBPLATFORM.h

@@ -53,7 +53,6 @@ typedef union _PCI_ADDR {
 	#define IMC_ENABLE_OVER_WRITE        0x01
 #endif
 
-#include <console/console.h>
 #include "AmdSbLib.h"
 #include "Amd.h"
 #include <SB800.h>

src/southbridge/amd/cimx/sb900/SbPlatform.h

@@ -49,7 +49,6 @@ typedef union _PCI_ADDR {
 #endif
 #define FIXUP_PTR(ptr)  ptr
 
-#include <console/console.h>
 #include "AmdSbLib.h"
 #include "Amd.h"
 #include "Hudson-2.h"

src/southbridge/amd/sb800/early_setup.c

@@ -17,9 +17,11 @@
 #define _SB800_EARLY_SETUP_C_
 
 #include <arch/io.h>
+#include <console/console.h>
 #include <reset.h>
 #include <southbridge/amd/common/amd_defs.h>
 #include <southbridge/amd/common/reset.h>
+
 #include "sb800.h"
 #include "smbus.c"
 

src/southbridge/nvidia/ck804/early_setup_car.c

@@ -17,6 +17,7 @@
  */
 
 #include <arch/io.h>
+#include <console/console.h>
 #include <reset.h>
 #include <southbridge/amd/common/reset.h>
 

src/southbridge/nvidia/mcp55/early_setup_car.c

@@ -17,6 +17,7 @@
 
 #include <arch/io.h>
 #include <delay.h>
+#include <console/console.h>
 
 #ifdef UNUSED_CODE
 int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);