From 351f1e68c45f4f092399bff6a4673b0e8d1d6f50 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Thu, 13 May 2021 11:34:14 +0530 Subject: [PATCH] soc/intel/alderlake: Update CPU and IGD Device IDs Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak --- src/include/device/pci_ids.h | 1 + src/soc/intel/alderlake/bootblock/report_platform.c | 2 ++ src/soc/intel/common/block/cpu/mp_init.c | 1 + src/soc/intel/common/block/graphics/graphics.c | 1 + src/soc/intel/common/block/include/intelblocks/mp_init.h | 1 + 5 files changed, 6 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a3ee558f76..1a9aa35645 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3812,6 +3812,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618 #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_1 0x46b0 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 26664268b0..78f02ecd97 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -23,6 +23,7 @@ static struct { const char *name; } cpu_table[] = { { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, + { CPUID_ALDERLAKE_P_B0, "Alderlake-P B0" }, { CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" }, }; @@ -98,6 +99,7 @@ static struct { { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, }; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 9619298771..7e8c199194 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -68,6 +68,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_B0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_M_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 0920a05848..fe89f86154 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -295,6 +295,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADL_GT1_8, PCI_DEVICE_ID_INTEL_ADL_GT1_9, PCI_DEVICE_ID_INTEL_ADL_P_GT2, + PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, PCI_DEVICE_ID_INTEL_ADL_S_GT1, PCI_DEVICE_ID_INTEL_ADL_M_GT1, 0, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 9038dd5823..3d8290f2bd 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_ELKHARTLAKE_B0 0x90661 #define CPUID_ALDERLAKE_S_A0 0x90670 #define CPUID_ALDERLAKE_P_A0 0x906a0 +#define CPUID_ALDERLAKE_P_B0 0x906a2 #define CPUID_ALDERLAKE_M_A0 0x906a1 /* * MP Init callback function to Find CPU Topology. This function is common