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mb/google/poppy/variants/nautilus: Change USB2 phy setting 

In order to pass USB2 eye diagram, some USB2 port PHY registers
needs to be changed.

Port1 (Type-A): USB2_PORT_SHORT
Port2 (BT): USB2_PORT_SHORT
Port6 (H1): USB2_PORT_SHORT
Port7 (Camera): USB2_PORT_SHORT

BUG=none
BRANCH=master
TEST=emerge-nautilus coreboot and do eye-diagram test
Signed-off-by: sh.kim <sh_.kim@samsung.com>

Change-Id: I174e5bf96a53bb210481fb88298d5341f6c11dec
Reviewed-on: https://review.coreboot.org/22686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
sh.kim 2017-12-01 16:09:50 +09:00 committed by Martin Roth
parent 2387f928e8
commit 35325e1688
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -163,11 +163,11 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1
register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2