This patch implements support for the Intel 3100 Development Kit
mainboard, aka "Mt. Arvon". Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ed Swierk
Stefan Reinauer
parent
a9faea8977
commit
354e2d3dc1
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Arastra, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License version 2 as
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## published by the Free Software Foundation.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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## Compute the location and size of where this firmware image
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## (coreboot plus bootloader) will live in the boot ROM chip
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of the coreboot bootloader
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of coreboot will start in the boot ROM
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up coreboot,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=131072
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/i3100
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device pci_domain 0 on
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device pci 00.0 on end # IMCH
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device pci 00.1 on end # IMCH error status
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device pci 01.0 on end # IMCH EDMA engine
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device pci 02.0 on end # PCIe port A/A0
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device pci 03.0 on end # PCIe port A1
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chip southbridge/intel/i3100
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# PIRQ line -> legacy IRQ mappings
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register "pirq_a_d" = "0x0b070a05"
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register "pirq_e_h" = "0x0a808080"
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device pci 1c.0 on end # PCIe port B0
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device pci 1c.1 on end # PCIe port B1
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device pci 1c.2 on end # PCIe port B2
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device pci 1c.3 on end # PCIe port B3
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device pci 1d.0 on end # USB (UHCI) 1
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device pci 1d.1 on end # USB (UHCI) 2
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device pci 1d.7 on end # USB (EHCI)
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device pci 1e.0 on end # PCI bridge
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device pci 1e.2 on end # audio
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device pci 1e.3 on end # modem
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device pci 1f.0 on # LPC bridge
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chip superio/intel/i3100
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device pnp 4e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.5 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end
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end
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMBus
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end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA479M
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device apic 0 on end
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end
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end
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end
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@ -0,0 +1,227 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Arastra, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License version 2 as
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## published by the Free Software Foundation.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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||||
##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses IRQ_SLOT_COUNT
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses _RAMBASE
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uses CONFIG_GDB_STUB
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CC
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uses HOSTCC
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uses CROSS_COMPILE
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uses OBJCOPY
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###
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### Build options
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###
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##
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## ROM_SIZE is the size of boot ROM that this board will use.
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##
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default ROM_SIZE = 2 * 1024 * 1024
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Delay timer options
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## Use timer2
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to reset the motherboard from coreboot
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=1
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=4
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default CONFIG_LOGICAL_CPUS=0
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_PART_NUMBER="Mt. Arvon"
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default MAINBOARD_VENDOR= "Intel"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
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default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
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###
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### Coreboot layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 32K heap
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##
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default HEAP_SIZE=0x8000
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###
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### Compute the location and size of where this firmware image
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### (coreboot plus bootloader) will live in the boot rom chip.
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###
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default FALLBACK_SIZE=131072
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##
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## coreboot C code runs at this location in RAM
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##
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default _RAMBASE=0x00004000
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##
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## Load the payload from the ROM
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##
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default CONFIG_ROM_PAYLOAD=1
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###
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### Defaults of options that you may want to override in the target config file
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###
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##
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## The default compiler
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##
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## Disable the gdb stub by default
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##
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default CONFIG_GDB_STUB=0
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the coreboot loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=5
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=5
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##
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## Select power on after power fail setting
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default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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### End Options.lb
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end
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@ -0,0 +1,124 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
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*
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <stdlib.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "southbridge/intel/i3100/i3100_early_smbus.c"
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#include "southbridge/intel/i3100/i3100_early_lpc.c"
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#include "northbridge/intel/i3100/raminit.h"
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#include "superio/intel/i3100/i3100.h"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "superio/intel/i3100/i3100_early_serial.c"
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#include "northbridge/intel/i3100/memory_initialized.c"
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#include "cpu/x86/bist.h"
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#define SIO_GPIO_BASE 0x680
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#define SIO_XBUS_BASE 0x4880
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||||
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
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#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
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||||
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||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
|
||||
/* nothing to do */
|
||||
}
|
||||
static inline int spd_read_byte(u16 device, u8 address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/i3100/raminit.c"
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||||
#include "sdram/generic_sdram.c"
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||||
#include "../jarrell/debug.c"
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||||
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
msr_t msr;
|
||||
u16 perf;
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x00, 0),
|
||||
.f1 = PCI_DEV(0, 0x00, 1),
|
||||
.f2 = PCI_DEV(0, 0x00, 2),
|
||||
.f3 = PCI_DEV(0, 0x00, 3),
|
||||
.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
|
||||
.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized()) {
|
||||
asm volatile ("jmp __cpu_reset");
|
||||
}
|
||||
}
|
||||
/* Set up the console */
|
||||
i3100_enable_superio();
|
||||
i3100_enable_serial(0x4e, I3100_SP1, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* print_pci_devices(); */
|
||||
enable_smbus();
|
||||
/* dump_spd_registers(); */
|
||||
|
||||
/* Enable SpeedStep and automatic thermal throttling */
|
||||
/* FIXME: move to Pentium M init code */
|
||||
msr = rdmsr(0x1a0);
|
||||
msr.lo |= (1 << 3) | (1 << 16);
|
||||
wrmsr(0x1a0, msr);
|
||||
msr = rdmsr(0x19d);
|
||||
msr.lo |= (1 << 16);
|
||||
wrmsr(0x19d, msr);
|
||||
|
||||
/* Set CPU frequency/voltage to maximum */
|
||||
/* FIXME: move to Pentium M init code */
|
||||
msr = rdmsr(0x198);
|
||||
perf = msr.hi & 0xffff;
|
||||
msr = rdmsr(0x199);
|
||||
msr.lo &= 0xffff0000;
|
||||
msr.lo |= perf;
|
||||
wrmsr(0x199, msr);
|
||||
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
/* dump_pci_devices(); */
|
||||
/* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
|
||||
/* dump_bar14(PCI_DEV(0, 0x00, 0)); */
|
||||
|
||||
ram_check(0, 1024 * 1024);
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Arastra, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
struct chip_operations mainboard_intel_mtarvon_ops;
|
||||
|
||||
struct mainboard_intel_mtarvon_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Arastra, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
(0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x2670, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x49, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Arastra, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_intel_mtarvon_ops = {
|
||||
CHIP_NAME("Intel Mt. Arvon Mainboard")
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Arastra, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/* This code is based on src/mainboard/intel/jarrell/mptable.c */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "Intel ";
|
||||
static const char productid[12] = "Mt. Arvon ";
|
||||
struct mp_config_table *mc;
|
||||
u8 bus_isa = 7;
|
||||
u8 bus_pci = 6;
|
||||
u8 bus_pcie_a = 1;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
/* Define bus numbers */
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, bus_pci, "PCI ");
|
||||
smp_write_bus(mc, bus_pcie_a, "PCI ");
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* IOAPIC handling */
|
||||
smp_write_ioapic(mc, 0x01, 0x20, 0xfec00000);
|
||||
|
||||
/* ISA backward compatibility interrupts */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, 0x01, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x01, 0x01, 0x01);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, 0x01, 0x02);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x03, 0x01, 0x03);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x04, 0x01, 0x04);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x06, 0x01, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x08, 0x01, 0x08);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x09, 0x01, 0x09);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0c, 0x01, 0x0c);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0d, 0x01, 0x0d);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0e, 0x01, 0x0e);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x0f, 0x01, 0x0f);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
/* Internal PCI devices */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
|
||||
|
||||
/* PCI slot */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pci, 0x00, 0x01, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pci, 0x01, 0x01, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pci, 0x02, 0x01, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pci, 0x03, 0x01, 0x13);
|
||||
|
||||
/* PCIe port A slot */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pcie_a, 0x00, 0x01, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pcie_a, 0x01, 0x01, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pcie_a, 0x02, 0x01, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pcie_a, 0x03, 0x01, 0x13);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Arastra, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License version 2 as
|
||||
## published by the Free Software Foundation.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
target mtarvon
|
||||
mainboard intel/mtarvon
|
||||
|
||||
## ROM_SIZE is the total number of bytes allocated for coreboot use
|
||||
## (normal AND fallback images and payloads).
|
||||
option ROM_SIZE = 2 * 1024 * 1024
|
||||
|
||||
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
|
||||
## not including any payload.
|
||||
option ROM_IMAGE_SIZE = 128 * 1024
|
||||
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image
|
||||
## (including payload) will use
|
||||
option FALLBACK_SIZE = ROM_SIZE
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
payload /tmp/filo.elf
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom ROM_SIZE "fallback"
|
||||
Loading…
Reference in New Issue