diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 87a98fb351..256fa06d8d 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -405,6 +405,26 @@ struct soc_intel_jasperlake_config {
 	 */
 	bool disable_external_bypass_vr;
 
+	/*
+	 * Core Display Clock Frequency selection, FSP UPD CdClock values + 1
+	 *
+	 * FSP will use the value to program clock frequency for core display if GOP
+	 * is not run. Ex: the Chromebook normal mode.
+	 * For the cases GOP is run, GOP will be in charge of the related register
+	 * settings.
+	 */
+	enum {
+		CD_CLOCK_172_8_MHZ = 1,
+		CD_CLOCK_180_MHZ   = 2,
+		CD_CLOCK_192_MHZ   = 3,
+		CD_CLOCK_307_MHZ   = 4,
+		CD_CLOCK_312_MHZ   = 5,
+		CD_CLOCK_552_MHZ   = 6,
+		CD_CLOCK_556_8_MHZ = 7,
+		CD_CLOCK_648_MHZ   = 8,
+		CD_CLOCK_652_8_MHZ = 9,
+	} cd_clock;
+
 };
 
 typedef struct soc_intel_jasperlake_config config_t;
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 085148f7b3..a5bcd55c8f 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -209,6 +209,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PchFivrExtVnnRailEnabledStates = 0;
 	}
 
+	/*
+	 * We intentionally want the default to be maximum value(0xff) to align with
+	 * FSP, so we reserve the `0` value here to mean auto instead, and shift the
+	 * other values by 1.
+	 *
+	 * Please refer to src/soc/intel/jasperlake/chip.h for the detail definition.
+	 */
+	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
+
 	/* Override/Fill FSP Silicon Param for mainboard */
 	mainboard_silicon_init_params(params);
 }
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
index dd7db9dae3..02d9d76616 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
@@ -875,11 +875,8 @@ typedef struct {
   UINT8                       PavpEnable;
 
 /** Offset 0x0436 - CdClock Frequency selection
-  0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180
-  Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz,
-  9: 652.8 Mhz
-  0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190
-  Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz
+  0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz,
+  7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz (Default)
 **/
   UINT8                       CdClock;