From 355fb2fb984cc264f4452d4bbffbd3666c71906e Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Thu, 9 Dec 2021 19:42:24 +0800
Subject: [PATCH] soc/intel/jasperlake: Add CdClock frequency config

Add a devicetree setting to configure the CdClock (Core Display Clock)
frequency through a FSP UPD. Because the value for this UPD's default
setting is non-zero and devicetree settings default to 0 if not set,
adapt the devicetree values so that the value for the UPD's default
setting is used when the devicetree setting is zero.

Also update the comment describing the FSP UPD in the header file
FspsUpd.h to match the correct CdClock definition.

BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log

Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/jasperlake/chip.h               | 20 +++++++++++++++++++
 src/soc/intel/jasperlake/fsp_params.c         |  9 +++++++++
 .../intel/fsp/fsp2_0/jasperlake/FspsUpd.h     |  7 ++-----
 3 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 87a98fb351..256fa06d8d 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -405,6 +405,26 @@ struct soc_intel_jasperlake_config {
 	 */
 	bool disable_external_bypass_vr;
 
+	/*
+	 * Core Display Clock Frequency selection, FSP UPD CdClock values + 1
+	 *
+	 * FSP will use the value to program clock frequency for core display if GOP
+	 * is not run. Ex: the Chromebook normal mode.
+	 * For the cases GOP is run, GOP will be in charge of the related register
+	 * settings.
+	 */
+	enum {
+		CD_CLOCK_172_8_MHZ = 1,
+		CD_CLOCK_180_MHZ   = 2,
+		CD_CLOCK_192_MHZ   = 3,
+		CD_CLOCK_307_MHZ   = 4,
+		CD_CLOCK_312_MHZ   = 5,
+		CD_CLOCK_552_MHZ   = 6,
+		CD_CLOCK_556_8_MHZ = 7,
+		CD_CLOCK_648_MHZ   = 8,
+		CD_CLOCK_652_8_MHZ = 9,
+	} cd_clock;
+
 };
 
 typedef struct soc_intel_jasperlake_config config_t;
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 085148f7b3..a5bcd55c8f 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -209,6 +209,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PchFivrExtVnnRailEnabledStates = 0;
 	}
 
+	/*
+	 * We intentionally want the default to be maximum value(0xff) to align with
+	 * FSP, so we reserve the `0` value here to mean auto instead, and shift the
+	 * other values by 1.
+	 *
+	 * Please refer to src/soc/intel/jasperlake/chip.h for the detail definition.
+	 */
+	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
+
 	/* Override/Fill FSP Silicon Param for mainboard */
 	mainboard_silicon_init_params(params);
 }
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
index dd7db9dae3..02d9d76616 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
@@ -875,11 +875,8 @@ typedef struct {
   UINT8                       PavpEnable;
 
 /** Offset 0x0436 - CdClock Frequency selection
-  0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180
-  Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz,
-  9: 652.8 Mhz
-  0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190
-  Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz
+  0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz,
+  7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz (Default)
 **/
   UINT8                       CdClock;