From 35605d689a50e8ed0ce707171acf3bb69c024b7c Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 24 Apr 2021 11:54:01 +0200
Subject: [PATCH] sb/intel/lynxpoint: Add and use power state bit macros

Tested with BUILD_TIMELESS=1, Google Wolf remains identical.

Change-Id: Id85b76c0aaf481f99f55a9ce6d813ff32753e588
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
 src/southbridge/intel/lynxpoint/elog.c | 30 +++++++++++++-------------
 src/southbridge/intel/lynxpoint/pch.h  | 11 ++++++++++
 2 files changed, 26 insertions(+), 15 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c
index 3ce765d1f5..839773a34d 100644
--- a/src/southbridge/intel/lynxpoint/elog.c
+++ b/src/southbridge/intel/lynxpoint/elog.c
@@ -15,15 +15,15 @@ static void pch_log_standard_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg)
 	u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en;
 
 	/* PME (TODO: determine wake device) */
-	if (gpe0_sts & (1 << 11))
+	if (gpe0_sts & PME_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
 
 	/* Internal PME (TODO: determine wake device) */
-	if (gpe0_sts & (1 << 13))
+	if (gpe0_sts & PME_B0_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
 
 	/* SMBUS Wake */
-	if (gpe0_sts & (1 << 7))
+	if (gpe0_sts & SMB_WAK_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
 }
 
@@ -108,39 +108,39 @@ void pch_log_state(void)
 	gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
 
 	/* PWR_FLR Power Failure */
-	if (gen_pmcon_2 & (1 << 0))
+	if (gen_pmcon_2 & PWROK_FLR)
 		elog_add_event(ELOG_TYPE_POWER_FAIL);
 
 	/* SUS Well Power Failure */
-	if (gen_pmcon_3 & (1 << 14))
+	if (gen_pmcon_3 & SUS_PWR_FLR)
 		elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
 
 	/* SYS_PWROK Failure */
-	if (gen_pmcon_2 & (1 << 1))
+	if (gen_pmcon_2 & SYSPWR_FLR)
 		elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
 
 	/* PWROK Failure */
-	if (gen_pmcon_2 & (1 << 0))
+	if (gen_pmcon_2 & PWROK_FLR)
 		elog_add_event(ELOG_TYPE_PWROK_FAIL);
 
 	/* Second TCO Timeout */
-	if (tco2_sts & (1 << 1))
+	if (tco2_sts & SECOND_TO_STS)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */
-	if (pm1_sts & (1 << 11))
+	if (pm1_sts & PRBTNOR_STS)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
 
 	/* System Reset Status (reset button pushed) */
-	if (gen_pmcon_2 & (1 << 4))
+	if (gen_pmcon_2 & SYSTEM_RESET_STS)
 		elog_add_event(ELOG_TYPE_RESET_BUTTON);
 
 	/* General Reset Status */
-	if (gen_pmcon_3 & (1 << 9))
+	if (gen_pmcon_3 & GEN_RST_STS)
 		elog_add_event(ELOG_TYPE_SYSTEM_RESET);
 
 	/* ACPI Wake */
-	if (pm1_sts & (1 << 15))
+	if (pm1_sts & WAK_STS)
 		elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
 				    acpi_is_wakeup_s3() ? 3 : 5);
 
@@ -149,15 +149,15 @@ void pch_log_state(void)
 	 */
 
 	/* Power Button */
-	if (pm1_sts & (1 << 8))
+	if (pm1_sts & PWRBTN_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
 
 	/* RTC */
-	if (pm1_sts & (1 << 10))
+	if (pm1_sts & RTC_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
 
 	/* PCI Express (TODO: determine wake device) */
-	if (pm1_sts & (1 << 14))
+	if (pm1_sts & PCIEXPWAK_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
 
 	/* GPE */
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 955eb7249f..763a6ca2a6 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -204,8 +204,18 @@ void mainboard_config_rcba(void);
 #define SERIRQ_CNTL		0x64
 
 #define GEN_PMCON_1		0xa0
+#define  SMI_LOCK		(1 << 4)
 #define GEN_PMCON_2		0xa2
+#define  SYSTEM_RESET_STS	(1 << 4)
+#define  THERMTRIP_STS		(1 << 3)
+#define  SYSPWR_FLR		(1 << 1)
+#define  PWROK_FLR		(1 << 0)
 #define GEN_PMCON_3		0xa4
+#define  SUS_PWR_FLR		(1 << 14)
+#define  GEN_RST_STS		(1 << 9)
+#define  RTC_BATTERY_DEAD	(1 << 2)
+#define  PWR_FLR		(1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
 #define PMIR			0xac
 #define  PMIR_CF9LOCK		(1 << 31)
 #define  PMIR_CF9GR		(1 << 20)
@@ -615,6 +625,7 @@ void mainboard_config_rcba(void);
 #define TCO1_STS	0x64
 #define   DMISCI_STS	(1 << 9)
 #define TCO2_STS	0x66
+#define   SECOND_TO_STS	(1 << 1)
 #define ALT_GP_SMI_EN2	0x5c
 #define ALT_GP_SMI_STS2	0x5e