haswell: Fix up GPU power management setup
New/more magic values from latest ref code. Change-Id: Ia2655333b4daca86c2f2a76f5edcd55cdaf3f851 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61334 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4356 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie
Stefan Reinauer
parent
118d105a37
commit
356833d0b5
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@ -24,10 +24,69 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <cpu/intel/haswell/haswell.h>
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#include "chip.h"
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#include "haswell.h"
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struct gt_reg {
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u32 reg;
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u32 andmask;
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u32 ormask;
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};
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static const struct gt_reg haswell_gt_setup[] = {
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/* Enable Counters */
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{ 0x0a248, 0x00000000, 0x00000016 },
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{ 0x0a000, 0x00000000, 0x00070020 },
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{ 0x0a180, 0xff3fffff, 0x15000000 },
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/* Enable DOP Clock Gating */
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{ 0x09424, 0x00000000, 0x000003fd },
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/* Enable Unit Level Clock Gating */
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{ 0x09400, 0x00000000, 0x00000080 },
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{ 0x09404, 0x00000000, 0x40401000 },
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{ 0x09408, 0x00000000, 0x00000000 },
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{ 0x0940c, 0x00000000, 0x02000001 },
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{ 0x0a008, 0x00000000, 0x08000000 },
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/* Wake Rate Limits */
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{ 0x0a090, 0xffffffff, 0x00000000 },
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{ 0x0a098, 0xffffffff, 0x03e80000 },
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{ 0x0a09c, 0xffffffff, 0x00280000 },
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{ 0x0a0a8, 0xffffffff, 0x0001e848 },
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{ 0x0a0ac, 0xffffffff, 0x00000019 },
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/* Render/Video/Blitter Idle Max Count */
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{ 0x02054, 0x00000000, 0x0000000a },
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{ 0x12054, 0x00000000, 0x0000000a },
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{ 0x22054, 0x00000000, 0x0000000a },
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/* RC Sleep / RCx Thresholds */
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{ 0x0a0b0, 0xffffffff, 0x00000000 },
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{ 0x0a0b4, 0xffffffff, 0x000003e8 },
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{ 0x0a0b8, 0xffffffff, 0x0000c350 },
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/* RP Settings */
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{ 0x0a010, 0xffffffff, 0x000f4240 },
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{ 0x0a014, 0xffffffff, 0x12060000 },
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{ 0x0a02c, 0xffffffff, 0x0000e808 },
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{ 0x0a030, 0xffffffff, 0x0003bd08 },
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{ 0x0a068, 0xffffffff, 0x000101d0 },
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{ 0x0a06c, 0xffffffff, 0x00055730 },
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{ 0x0a070, 0xffffffff, 0x0000000a },
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/* RP Control */
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{ 0x0a024, 0x00000000, 0x00000b92 },
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/* HW RC6 Control */
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{ 0x0a090, 0x00000000, 0x88040000 },
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/* Video Frequency Request */
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{ 0x0a00c, 0x00000000, 0x08000000 },
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{ 0 },
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};
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static const struct gt_reg haswell_gt_lock[] = {
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{ 0x0a248, 0xffffffff, 0x80000000 },
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{ 0x0a004, 0xffffffff, 0x00000010 },
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{ 0x0a080, 0xffffffff, 0x00000004 },
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{ 0x0a180, 0xffffffff, 0x80000000 },
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{ 0 },
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};
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/* some vga option roms are used for several chipsets but they only have one
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* PCI ID in their header. If we encounter such an option rom, we need to do
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* the mapping ourselfes
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@ -72,6 +131,24 @@ static inline void gtt_write(u32 reg, u32 data)
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write32(gtt_res->base + reg, data);
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}
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static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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{
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u32 val = gtt_read(reg);
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val &= andmask;
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val |= ormask;
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gtt_write(reg, val);
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}
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static inline void gtt_write_regs(const struct gt_reg *gt)
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{
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for (; gt && gt->reg; gt++) {
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if (gt->andmask)
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gtt_rmw(gt->reg, gt->andmask, gt->ormask);
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else
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gtt_write(gt->reg, gt->ormask);
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}
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}
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#define GTT_RETRY 1000
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static int gtt_poll(u32 reg, u32 mask, u32 value)
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{
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@ -114,30 +191,26 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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gtt_write(0x0a188, 0x00010001);
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gtt_poll(0x130044, 1 << 0, 1 << 0);
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/* Enable counters and lock */
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gtt_write(0x0a248, 0x80000016);
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gtt_write(0x0a000, 0x00070020);
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gtt_write(0x0a180, 0xc5000020);
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/* GT Settings */
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gtt_write_regs(haswell_gt_setup);
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/* Enable DOP clock gating */
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gtt_write(0x09424, 0x00000001);
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/* Wait for Mailbox Ready */
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gtt_poll(0x138124, (1 << 31), (0 << 31));
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/* Mailbox Data - RC6 VIDS */
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gtt_write(0x138128, 0x00000000);
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/* Mailbox Command */
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gtt_write(0x138124, 0x80000004);
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/* Wait for Mailbox Ready */
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gtt_poll(0x138124, (1 << 31), (0 << 31));
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/* Enable unit level clock gating */
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gtt_write(0x09400, 0x00000080);
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gtt_write(0x09404, 0x40401000);
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gtt_write(0x09408, 0x00000000);
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gtt_write(0x0940c, 0x02000001);
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/* Configure max ilde count */
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gtt_write(0x02054, 0x0000000a);
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gtt_write(0x12054, 0x0000000a);
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gtt_write(0x22054, 0x0000000a);
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gtt_write(0x0a008, 0x80000000);
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gtt_write(0x0a024, 0x00000b92);
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/* Enable PM Interrupts */
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gtt_write(0x4402c, 0x03000076);
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/* Enable RC6 in idle */
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gtt_write(0x0a094, 0x00040000);
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/* PM Lock Settings */
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gtt_write_regs(haswell_gt_lock);
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}
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static void gma_setup_panel(struct device *dev)
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@ -269,9 +342,47 @@ static void gma_setup_panel(struct device *dev)
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static void gma_pm_init_post_vbios(struct device *dev)
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{
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int cdclk = 0;
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int devid = pci_read_config16(dev, PCI_DEVICE_ID);
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int gpu_is_ulx = 0;
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if (devid == 0x0a0e || devid == 0x0a1e)
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gpu_is_ulx = 1;
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/* CD Frequency */
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if (gtt_read(0x42014) & 0x1000000) {
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cdclk = 0; /* only 450mhz */
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} else {
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cdclk = 2; /* 337.5mhz, 450mhz, or 540mhz */
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if (gpu_is_ulx)
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cdclk = 0; /* only 337.5mhz */
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/* TODO: this check does not seem right... */
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if (haswell_is_ult() &&
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haswell_stepping() < HASWELL_STEPPING_MOBILE_D0)
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cdclk = 0; /* only 450mhz */
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else
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cdclk = 1; /* 337.5mhz and 450mhz */
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}
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if (gpu_is_ulx || cdclk != 0)
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gtt_rmw(0x130040, 0xf7ffffff, 0x04000000);
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else
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gtt_rmw(0x130040, 0xf3ffffff, 0x00000000);
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/* More magic */
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if (haswell_is_ult() || gpu_is_ulx) {
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if (cdclk == 1 && gpu_is_ulx == 0)
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gtt_write(0x138128, 0x00000000);
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else
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gtt_write(0x138128, 0x00000001);
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gtt_write(0x13812c, 0x00000000);
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gtt_write(0x138124, 0x80000017);
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}
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/* Disable Force Wake */
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gtt_write(0x0a188, 0x00010000);
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gtt_poll(0x130044, 1 << 0, 0 << 0);
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gtt_write(0x0a188, 0x00000001);
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}
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static void gma_func0_init(struct device *dev)
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