soc/mediatek/mt8188: Add support for MIPI panel
We need to add DSI and MIPI_TX settings to support MIPI panel. BUG=b:244208960 TEST=emerge-geralt coreboot Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70184 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -39,6 +39,7 @@ ramstage-y += ../common/dfd.c
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ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
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ramstage-y += ../common/dpm.c
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ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
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ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
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ramstage-y += ../common/emi.c
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ramstage-y += ../common/mcu.c
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ramstage-y += ../common/mcupm.c
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@ -77,6 +77,7 @@ enum {
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I2C3_BASE = IO_PHYS + 0x01282000,
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SFLASH_REG_BASE = IO_PHYS + 0x0132C000,
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IOCFG_RM_BASE = IO_PHYS + 0x01C00000,
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MIPITX_BASE = IO_PHYS + 0x01C80000,
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I2C1_BASE = IO_PHYS + 0x01E00000,
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I2C4_BASE = IO_PHYS + 0x01E01000,
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IOCFG_LT_BASE = IO_PHYS + 0x01E10000,
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@ -95,6 +96,7 @@ enum {
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DISP_AAL0_BASE = IO_PHYS + 0x0C005000,
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DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000,
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DISP_DITHER0_BASE = IO_PHYS + 0x0C007000,
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DSI0_BASE = IO_PHYS + 0x0C008000,
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DISP_OVL1_BASE = IO_PHYS + 0x0C00A000,
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DP_INTF0_BASE = IO_PHYS + 0x0C015000,
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DISP_MUTEX_BASE = IO_PHYS + 0x0C016000,
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@ -0,0 +1,56 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_MT8188_DSI_H
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#define SOC_MEDIATEK_MT8188_DSI_H
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#include <soc/dsi_common.h>
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#include <soc/dsi_register_v2.h>
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/* DSI features */
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#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
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#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
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#define MTK_DSI_DATA_RATE_MIN_MHZ 125
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#define MTK_DSI_HAVE_SIZE_CON 1
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#define PIXEL_STREAM_CUSTOM_HEADER 0xb
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/* MIPITX is SOC specific and cannot live in common. */
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/* MIPITX_REG */
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struct mipi_tx_regs {
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u32 reserved0[3];
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u32 lane_con;
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u32 reserved1[6];
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u32 pll_pwr;
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u32 pll_con0;
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u32 pll_con1;
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u32 pll_con2;
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u32 pll_con3;
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u32 pll_con4;
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u32 reserved2[65];
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u32 d2_sw_ctl_en;
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u32 reserved3[63];
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u32 d0_sw_ctl_en;
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u32 reserved4[56];
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u32 ck_ckmode_en;
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u32 reserved5[6];
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u32 ck_sw_ctl_en;
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u32 reserved6[63];
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u32 d1_sw_ctl_en;
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u32 reserved7[63];
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u32 d3_sw_ctl_en;
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};
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check_member(mipi_tx_regs, pll_con4, 0x3c);
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check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
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static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
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/* Register values */
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#define DSI_CK_CKMODE_EN BIT(0)
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#define DSI_SW_CTL_EN BIT(0)
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#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
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#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
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#define RG_DSI_PLL_EN BIT(4)
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#define RG_DSI_PLL_POSDIV (0x7 << 8)
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#endif
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