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skylake: Show SPI controller if enabled in devicetree.cb 

Unhide the SPI controller PCI device if it is enabled in
devicetree.cb so flashrom can do its job.

BUG=chrome-os-partner:37711
BRANCH=none
TEST=run flashrom -r on glados

Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245
Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284948
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10986
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2015-07-13 09:34:37 -07:00 committed by Patrick Georgi
parent 0893e29755
commit 356cabbe35
2 changed files with 4 additions and 3 deletions
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3
src/soc/intel/skylake/chip.h
View File

@ -199,9 +199,6 @@ struct soc_intel_skylake_config {
/* Integrated Sensor */ /* Integrated Sensor */
u8 IshEnable; u8 IshEnable;
/* SPI related */
u8 ShowSpiController;
u8 PttSwitch; u8 PttSwitch;
u8 HeciTimeouts; u8 HeciTimeouts;
u8 HsioMessaging; u8 HsioMessaging;

4
src/soc/intel/skylake/romstage/romstage.c
View File

@ -111,6 +111,10 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params)
params->IoBufferOwnership = config->IoBufferOwnership; params->IoBufferOwnership = config->IoBufferOwnership;
params->DspEnable = config->DspEnable; params->DspEnable = config->DspEnable;
params->XdciEnable = config->XdciEnable; params->XdciEnable = config->XdciEnable;
/* Show SPI controller if enabled in devicetree.cb */
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
} }
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,