nb/intel/i945: Put names to northbridge PCI devices
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Felix Held
parent
ce55b36c99
commit
3580d816e6
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@ -18,5 +18,5 @@ void bootblock_early_northbridge_init(void)
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* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
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*/
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
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pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
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}
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@ -15,7 +15,7 @@
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int i945_silicon_revision(void)
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{
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return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION);
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return pci_read_config8(HOST_BRIDGE, PCI_CLASS_REVISION);
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}
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static void i945m_detect_chipset(void)
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@ -23,7 +23,7 @@ static void i945m_detect_chipset(void)
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u8 reg8;
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printk(BIOS_INFO, "\n");
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
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reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4;
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switch (reg8) {
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case 1:
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printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
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@ -46,7 +46,7 @@ static void i945m_detect_chipset(void)
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printk(BIOS_INFO, " Chipset\n");
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printk(BIOS_DEBUG, "(G)MCH capable of up to FSB ");
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5;
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reg8 = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0xe0) >> 5;
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switch (reg8) {
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case 2:
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printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */
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@ -63,7 +63,7 @@ static void i945m_detect_chipset(void)
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printk(BIOS_DEBUG, "\n");
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printk(BIOS_DEBUG, "(G)MCH capable of ");
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
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reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07);
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switch (reg8) {
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case 2:
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printk(BIOS_DEBUG, "up to DDR2-667");
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@ -89,8 +89,8 @@ static void i945_detect_chipset(void)
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printk(BIOS_INFO, "\nIntel(R) ");
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reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4)
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| ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
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reg8 = ((pci_read_config8(HOST_BRIDGE, 0xe7) >> 5) & 4)
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| ((pci_read_config8(HOST_BRIDGE, 0xe4) >> 4) & 3);
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switch (reg8) {
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case 0:
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case 1:
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@ -116,7 +116,7 @@ static void i945_detect_chipset(void)
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printk(BIOS_INFO, " Chipset\n");
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printk(BIOS_DEBUG, "(G)MCH capable of ");
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
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reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07);
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switch (reg8) {
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case 0:
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case 2:
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@ -144,10 +144,10 @@ static void i945_setup_bars(void)
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printk(BIOS_DEBUG, "Setting up static northbridge registers...");
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/* Set up all hardcoded northbridge BARs */
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pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
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pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1);
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pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
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pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
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pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
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/* vram size from CMOS option */
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if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS)
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@ -155,25 +155,25 @@ static void i945_setup_bars(void)
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/* make sure no invalid setting is used */
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if (gfxsize > 6)
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gfxsize = 2;
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pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
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pci_write_config16(HOST_BRIDGE, GGC, ((gfxsize + 1) << 4));
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/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
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which requires to have TSEG_BASE aligned to TSEG_SIZE. */
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pci_update_config8(PCI_DEV(0, 0, 0), ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
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pci_update_config8(HOST_BRIDGE, ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
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pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
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pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
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pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
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pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
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pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
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pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
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pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
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printk(BIOS_DEBUG, " done.\n");
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/* Wait for MCH BAR to come up */
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printk(BIOS_DEBUG, "Waiting for MCHBAR to come up...");
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if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */
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if ((pci_read_config32(HOST_BRIDGE, 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */
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do {
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reg8 = *(volatile u8 *)0xfed40000;
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} while (!(reg8 & 0x80));
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@ -245,7 +245,7 @@ static void i945_setup_egress_port(void)
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}
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/* Is internal graphics enabled? */
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if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
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if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
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MCHBAR32(MMARB1) |= (1 << 17);
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/* Assign Virtual Channel ID 1 to VC1 */
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@ -405,7 +405,7 @@ static void i945_setup_dmi_rcrb(void)
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#endif
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DMIBAR32(0x204) = reg32;
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if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
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if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
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printk(BIOS_DEBUG, "Internal graphics: enabled\n");
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DMIBAR32(0x200) |= (1 << 21);
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} else {
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@ -501,7 +501,7 @@ static void i945_setup_pci_express_x16(void)
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printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
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pci_or_config16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0);
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pci_or_config16(HOST_BRIDGE, DEVEN, DEVEN_D1F0);
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pci_and_config32(p2peg, PEGCC, ~(1 << 8));
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@ -600,9 +600,9 @@ static void i945_setup_pci_express_x16(void)
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if (reg32 == 0x030000) {
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printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
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reg16 = (1 << 1);
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pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16);
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pci_write_config16(HOST_BRIDGE, GGC, reg16);
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pci_and_config32(PCI_DEV(0, 0x0, 0), DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1));
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pci_and_config32(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1));
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}
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/* Enable GPEs: PMEGPE, HPGPE, GENGPE */
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@ -698,7 +698,7 @@ disable_pciexpress_x16_link:
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printk(BIOS_DEBUG, "ok\n");
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/* Finally: Disable the PCI config header */
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pci_and_config16(PCI_DEV(0, 0x00, 0), DEVEN, ~DEVEN_D1F0);
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pci_and_config16(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0);
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}
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static void i945_setup_root_complex_topology(void)
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@ -738,7 +738,7 @@ static void i945_setup_root_complex_topology(void)
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DMIBAR32(DMILE2A) = DEFAULT_EPBAR;
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/* PCI Express x16 Port Root Topology */
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if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) {
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if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) {
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pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR);
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pci_or_config32(p2peg, LE1D, 1 << 0);
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}
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@ -777,7 +777,7 @@ static void ich7_setup_pci_express(void)
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void i945_early_initialization(void)
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{
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/* Print some chipset specific information */
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switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) {
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switch (pci_read_config32(HOST_BRIDGE, 0)) {
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case 0x27708086: /* 82945G/GZ/GC/P/PL */
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i945_detect_chipset();
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break;
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@ -31,6 +31,7 @@
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#define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7)
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#define EPBAR 0x40
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#define MCHBAR 0x44
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@ -88,6 +89,7 @@
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define IGD_DEV PCI_DEV(0, 2, 0)
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#define GMADR 0x18
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#define GTTADR 0x1c
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@ -36,20 +36,20 @@ static uintptr_t northbridge_get_tseg_base(void)
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{
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uintptr_t tom;
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if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
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if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
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/* IGD enabled, get top of Memory from BSM register */
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tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
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tom = pci_read_config32(IGD_DEV, BSM);
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else
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tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
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tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf7) << 24;
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/* subtract TSEG size */
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tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC));
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tom -= decode_tseg_size(pci_read_config8(HOST_BRIDGE, ESMRAMC));
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return tom;
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}
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
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const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
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return decode_tseg_size(esmramc);
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}
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@ -137,7 +137,7 @@ static int sdram_capabilities_max_supported_memory_frequency(void)
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return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
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#endif
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reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
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reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */
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reg32 &= (7 << 0);
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switch (reg32) {
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@ -161,7 +161,7 @@ static int sdram_capabilities_interleave(void)
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{
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u32 reg32;
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reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
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reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */
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reg32 >>= 25;
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reg32 &= 1;
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@ -177,7 +177,7 @@ static int sdram_capabilities_dual_channel(void)
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{
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u32 reg32;
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reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
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reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */
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reg32 >>= 24;
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reg32 &= 1;
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@ -188,7 +188,7 @@ static int sdram_capabilities_enhanced_addressing_xor(void)
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{
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u8 reg8;
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reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
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reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */
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reg8 &= (1 << 7);
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return (!reg8);
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@ -203,7 +203,7 @@ static int sdram_capabilities_core_frequencies(void)
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{
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u8 reg8;
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reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
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reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */
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reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
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reg8 >>= 1;
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@ -1186,13 +1186,13 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
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tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud);
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pci_write_config8(PCI_DEV(0, 0, 0), TOLUD, tolud);
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pci_write_config8(HOST_BRIDGE, TOLUD, tolud);
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printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
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printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
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printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0, 0, 0), TOLUD));
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printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(HOST_BRIDGE, TOLUD));
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pci_write_config16(PCI_DEV(0, 0, 0), TOM, tom);
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pci_write_config16(HOST_BRIDGE, TOM, tom);
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return 0;
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}
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@ -1625,7 +1625,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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/* Gate graphics hardware for frequency change */
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reg8 = (1 << 3) | (1 << 1); /* disable crclk, gate cdclk */
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pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
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pci_write_config8(IGD_DEV, GCFC + 1, reg8);
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/* Get graphics frequency capabilities */
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reg8 = sdram_capabilities_core_frequencies();
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@ -1651,7 +1651,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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if (freq != CRCLK_400MHz) {
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/* What chipset are we? Force 166MHz for GMS */
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
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reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4;
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if (reg8 == 2)
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freq = CRCLK_166MHz;
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}
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@ -1701,10 +1701,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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sysinfo->clkcfg_bit7 = 0;
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/* Graphics Core Render Clock */
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pci_update_config16(PCI_DEV(0, 2, 0), GCFC, ~((7 << 0) | (1 << 13)), freq);
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pci_update_config16(IGD_DEV, GCFC, ~((7 << 0) | (1 << 13)), freq);
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/* Graphics Core Display Clock */
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reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC);
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reg8 = pci_read_config8(IGD_DEV, GCFC);
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reg8 &= ~((1 << 7) | (7 << 4));
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if (voltage == VOLTAGE_1_05) {
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@ -1714,19 +1714,19 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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reg8 |= CDCLK_320MHz;
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printk(BIOS_DEBUG, " Display: 320MHz\n");
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}
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pci_write_config8(PCI_DEV(0, 2, 0), GCFC, reg8);
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pci_write_config8(IGD_DEV, GCFC, reg8);
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reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1);
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reg8 = pci_read_config8(IGD_DEV, GCFC + 1);
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reg8 |= (1 << 3) | (1 << 1);
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pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
|
||||
pci_write_config8(IGD_DEV, GCFC + 1, reg8);
|
||||
|
||||
reg8 |= 0x0f;
|
||||
pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
|
||||
pci_write_config8(IGD_DEV, GCFC + 1, reg8);
|
||||
|
||||
/* Ungate core render and display clocks */
|
||||
reg8 &= 0xf0;
|
||||
pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
|
||||
pci_write_config8(IGD_DEV, GCFC + 1, reg8);
|
||||
}
|
||||
|
||||
static void sdram_program_memory_frequency(struct sys_info *sysinfo)
|
||||
|
|
@ -2185,7 +2185,11 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
reg16 |= (4 << 11);
|
||||
MCHBAR16(CPCTL) = reg16;
|
||||
|
||||
#if 0
|
||||
if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
|
||||
#else
|
||||
if (i945_silicon_revision() != 0) {
|
||||
#endif
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 667:
|
||||
MCHBAR32(HGIPMC2) = 0x0d590d59;
|
||||
|
|
@ -2260,9 +2264,9 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
MCHBAR32(FSBPMC4) |= (1 << 4);
|
||||
}
|
||||
|
||||
pci_or_config8(PCI_DEV(0, 0x0, 0), 0xfc, 1 << 4);
|
||||
pci_or_config8(HOST_BRIDGE, 0xfc, 1 << 4);
|
||||
|
||||
pci_or_config8(PCI_DEV(0, 0x2, 0), 0xc1, 1 << 2);
|
||||
pci_or_config8(IGD_DEV, 0xc1, 1 << 2);
|
||||
|
||||
if (integrated_graphics) {
|
||||
MCHBAR16(MIPMC4) = 0x04f8;
|
||||
|
|
@ -2702,7 +2706,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
|
|||
if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
|
||||
sdram_program_graphics_frequency(&sysinfo);
|
||||
else
|
||||
pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
|
||||
pci_write_config16(IGD_DEV, GCFC, 0x0534);
|
||||
|
||||
/* Program System Memory Frequency */
|
||||
sdram_program_memory_frequency(&sysinfo);
|
||||
|
|
|
|||
Loading…
Reference in New Issue