From 3585dc5be4ddf01ee61907d963e070386d31d054 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 17 May 2021 18:19:22 -0700
Subject: [PATCH] mb/intel/adlrvp_m: add ec device entry to devicetree

TEST=Boot to OS and verify acpi tables.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb  | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
index 80450e7cd4..68a1bfa1d6 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
@@ -1,5 +1,12 @@
 chip soc/intel/alderlake
 	device domain 0 on
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end # eSPI
 		device pci 1f.2 hidden
 
 			# The pmc_mux chip driver is a placeholder for the