submit ati rage driver.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
5a56d51d54
commit
35902425b8
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@ -0,0 +1 @@
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driver xlinit.o
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@ -0,0 +1,409 @@
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/*
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* ATI Frame Buffer Device Driver Core Definitions
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*/
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#define u32 uint32_t
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#define u16 uint16_t
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#define u8 uint8_t
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#define u_int uint32_t
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#define EINVAL -1
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#define readb(addr) (*(volatile unsigned char *) (addr))
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#define readw(addr) (*(volatile unsigned short *) (addr))
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#define readl(addr) (*(volatile unsigned int *) (addr))
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#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b))
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#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b))
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#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b))
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#define max(x,y) (x>=y)?x:y
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/*
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* Elements of the hardware specific atyfb_par structure
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*/
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#if 0
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struct crtc {
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u32 vxres;
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u32 vyres;
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u32 xoffset;
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u32 yoffset;
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u32 bpp;
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u32 h_tot_disp;
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u32 h_sync_strt_wid;
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u32 v_tot_disp;
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u32 v_sync_strt_wid;
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u32 off_pitch;
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u32 gen_cntl;
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u32 dp_pix_width; /* acceleration */
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u32 dp_chain_mask; /* acceleration */
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};
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struct pll_514 {
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u8 m;
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u8 n;
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};
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struct pll_18818
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{
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u32 program_bits;
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u32 locationAddr;
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u32 period_in_ps;
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u32 post_divider;
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};
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#endif
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struct pll_ct {
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u8 pll_ref_div;
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u8 pll_gen_cntl;
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u8 mclk_fb_div;
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u8 mclk_fb_mult; /* 2 or 4 */
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u8 sclk_fb_div;
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u8 pll_vclk_cntl;
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u8 vclk_post_div;
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u8 vclk_fb_div;
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u8 pll_ext_cntl;
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u8 spll_cntl2;
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u32 dsp_config; /* Mach64 GTB DSP */
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u32 dsp_on_off; /* Mach64 GTB DSP */
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u8 mclk_post_div_real;
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u8 xclk_post_div_real;
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u8 vclk_post_div_real;
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};
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union aty_pll {
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struct pll_ct ct;
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#if 0
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struct pll_514 ibm514;
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struct pll_18818 ics2595;
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#endif
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};
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/*
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* The hardware parameters for each card
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*/
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#if 0
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struct atyfb_par {
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struct crtc crtc;
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union aty_pll pll;
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u32 accel_flags;
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};
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struct aty_cursor {
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int enable;
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int on;
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int vbl_cnt;
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int blink_rate;
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u32 offset;
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struct {
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u16 x, y;
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} pos, hot, size;
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u32 color[2];
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u8 bits[8][64];
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u8 mask[8][64];
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u8 *ram;
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struct timer_list *timer;
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};
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#endif
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struct fb_info_aty {
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#if 0
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struct fb_info fb_info;
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struct fb_info_aty *next;
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unsigned long ati_regbase_phys;
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#endif
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unsigned long ati_regbase;
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#if 0
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unsigned long frame_buffer_phys;
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unsigned long frame_buffer;
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unsigned long clk_wr_offset;
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struct pci_mmap_map *mmap_map;
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struct aty_cursor *cursor;
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struct aty_cmap_regs *aty_cmap_regs;
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struct { u8 red, green, blue, pad; } palette[256];
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struct atyfb_par default_par;
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struct atyfb_par current_par;
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#endif
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u32 features;
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u32 total_vram;
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u32 ref_clk_per;
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u32 pll_per;
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u32 mclk_per;
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u32 xclk_per;
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u8 bus_type;
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u8 ram_type;
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#if 0
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u8 mem_refresh_rate;
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#endif
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#if 0
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struct aty_dac_ops *dac_ops;
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struct aty_pll_ops *pll_ops;
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#endif
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#if 0
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struct display disp;
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struct display_switch dispsw;
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#endif
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#if 0
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union {
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#ifdef FBCON_HAS_CFB16
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u16 cfb16[16];
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#endif
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#ifdef FBCON_HAS_CFB24
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u32 cfb24[16];
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#endif
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#ifdef FBCON_HAS_CFB32
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u32 cfb32[16];
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#endif
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} fbcon_cmap;
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u8 blitter_may_be_busy;
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#ifdef __sparc__
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u8 mmaped;
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int open;
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int vtconsole;
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int consolecnt;
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#endif
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#ifdef CONFIG_PMAC_PBOOK
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unsigned char *save_framebuffer;
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unsigned long save_pll[64];
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#endif
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#endif
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};
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/*
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* ATI Mach64 features
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*/
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#define M64_HAS(feature) ((info)->features & (M64F_##feature))
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#define M64F_RESET_3D 0x00000001
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#define M64F_MAGIC_FIFO 0x00000002
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#define M64F_GTB_DSP 0x00000004
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#define M64F_FIFO_24 0x00000008
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#define M64F_SDRAM_MAGIC_PLL 0x00000010
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#define M64F_MAGIC_POSTDIV 0x00000020
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#define M64F_INTEGRATED 0x00000040
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#define M64F_CT_BUS 0x00000080
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#define M64F_VT_BUS 0x00000100
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#define M64F_MOBIL_BUS 0x00000200
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#define M64F_GX 0x00000400
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#define M64F_CT 0x00000800
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#define M64F_VT 0x00001000
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#define M64F_GT 0x00002000
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#define M64F_MAGIC_VRAM_SIZE 0x00004000
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#define M64F_G3_PB_1_1 0x00008000
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#define M64F_G3_PB_1024x768 0x00010000
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#define M64F_EXTRA_BRIGHT 0x00020000
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#define M64F_LT_SLEEP 0x00040000
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#define M64F_XL_DLL 0x00080000
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#define M64F_MFB_TIMES_4 0x00100000
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/*
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* Register access
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*/
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static inline u32 aty_ld_le32(int regindex,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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return in_le32((volatile u32 *)(info->ati_regbase+regindex));
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#else
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return readl (info->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_le32(int regindex, u32 val,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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out_le32 (info->ati_regbase+regindex, val);
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#else
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writel (val, info->ati_regbase + regindex);
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#endif
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}
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static inline u16 aty_ld_le16(int regindex,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#if defined(__mc68000__)
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return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex)));
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#else
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return readw (info->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_le16(int regindex, u16 val,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#if defined(__mc68000__)
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*((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val);
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#else
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writew (val, info->ati_regbase + regindex);
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#endif
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}
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static inline u8 aty_ld_8(int regindex,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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return in_8 (info->ati_regbase + regindex);
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#else
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return readb (info->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_8(int regindex, u8 val,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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out_8 (info->ati_regbase + regindex, val);
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#else
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writeb (val, info->ati_regbase + regindex);
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#endif
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}
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static inline u8 aty_ld_pll(int offset, const struct fb_info_aty *info)
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{
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u8 res;
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/* write addr byte */
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aty_st_8(CLOCK_CNTL + 1, (offset << 2), info);
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/* read the register value */
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res = aty_ld_8(CLOCK_CNTL + 2, info);
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return res;
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}
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/*
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* CT family only.
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*/
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static inline void aty_st_pll(int offset, u8 val,
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const struct fb_info_aty *info)
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{
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/* write addr byte */
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aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, info);
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/* write the register value */
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aty_st_8(CLOCK_CNTL + 2, val, info);
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aty_st_8(CLOCK_CNTL + 1, (offset << 2) & ~PLL_WR_EN, info);
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}
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/*
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* DAC operations
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*/
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#if 0
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struct aty_dac_ops {
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int (*set_dac)(const struct fb_info_aty *info, const union aty_pll *pll,
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u32 bpp, u32 accel);
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};
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extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
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extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
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extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
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extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
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static struct aty_dac_ops aty_dac_ct; /* Integrated */
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#endif
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/*
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* Clock operations
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*/
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#if 0
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struct aty_pll_ops {
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int (*var_to_pll)(const struct fb_info_aty *info, u32 vclk_per, u8 bpp,
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union aty_pll *pll);
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#if 0
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u32 (*pll_to_var)(const struct fb_info_aty *info,
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const union aty_pll *pll);
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void (*set_pll)(const struct fb_info_aty *info, const union aty_pll *pll);
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#endif
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};
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#endif
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#if 0
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extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
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extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
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extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
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extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
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extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
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extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
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static struct aty_pll_ops aty_pll_ct; /* Integrated */
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static void aty_set_pll_ct(const struct fb_info_aty *info,
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const union aty_pll *pll);
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static void aty_calc_pll_ct(const struct fb_info_aty *info,
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struct pll_ct *pll);
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#endif
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#if 0
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/*
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* Hardware cursor support
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*/
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extern struct aty_cursor *aty_init_cursor(struct fb_info_aty *fb);
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extern void atyfb_cursor(struct display *p, int mode, int x, int y);
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extern void aty_set_cursor_color(struct fb_info_aty *fb);
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extern void aty_set_cursor_shape(struct fb_info_aty *fb);
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extern int atyfb_set_font(struct display *d, int width, int height);
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/*
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* Hardware acceleration
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*/
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static inline void wait_for_fifo(u16 entries, const struct fb_info_aty *info)
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{
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while ((aty_ld_le32(FIFO_STAT, info) & 0xffff) >
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((u32)(0x8000 >> entries)));
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}
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static inline void wait_for_idle(struct fb_info_aty *info)
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{
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wait_for_fifo(16, info);
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while ((aty_ld_le32(GUI_STAT, info) & 1)!= 0);
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info->blitter_may_be_busy = 0;
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}
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extern void aty_reset_engine(const struct fb_info_aty *info);
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extern void aty_init_engine(const struct atyfb_par *par,
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struct fb_info_aty *info);
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extern void aty_rectfill(int dstx, int dsty, u_int width, u_int height,
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u_int color, struct fb_info_aty *info);
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/*
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* Text console acceleration
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*/
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extern const struct display_switch fbcon_aty8;
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extern const struct display_switch fbcon_aty16;
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extern const struct display_switch fbcon_aty24;
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extern const struct display_switch fbcon_aty32;
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,363 @@
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#define DEBUG_PLL 0
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/* FIXME: remove the FAIL definition */
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#define FAIL(x) do { printk_debug(x); return -EINVAL; } while (0)
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static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
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struct pll_ct *pll);
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static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp,
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struct pll_ct *pll);
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static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
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u8 bpp, union aty_pll *pll);
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#if 0
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static u32 aty_pll_ct_to_var(const struct fb_info_aty *info,
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const union aty_pll *pll);
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* PLL programming (Mach64 CT family)
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*/
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static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp,
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struct pll_ct *pll)
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{
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u32 dsp_xclks_per_row, dsp_loop_latency, dsp_precision, dsp_off, dsp_on;
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u32 xclks_per_row, fifo_off, fifo_on, y, fifo_size;
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u32 memcntl, n, t_pfc, t_rp, t_ras, t_rcd, t_crd, t_rcc, t_lat;
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#if DEBUG_PLL==1
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printk_debug("aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult);
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#endif
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/* (64*xclk/vclk/bpp)<<11 = xclocks_per_row<<11 */
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xclks_per_row = ((u32)pll->mclk_fb_mult * (u32)pll->mclk_fb_div *
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(u32)pll->vclk_post_div_real * 64) << 11;
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xclks_per_row /=
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(2 * (u32)pll->vclk_fb_div * (u32)pll->xclk_post_div_real * bpp);
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if (xclks_per_row < (1<<11))
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FAIL("Dotclock too high");
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if (M64_HAS(FIFO_24)) {
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fifo_size = 24;
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dsp_loop_latency = 0;
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} else {
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fifo_size = 32;
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dsp_loop_latency = 2;
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}
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dsp_precision = 0;
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y = (xclks_per_row*fifo_size)>>11;
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while (y) {
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y >>= 1;
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dsp_precision++;
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}
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dsp_precision -= 5;
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/* fifo_off<<6 */
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fifo_off = ((xclks_per_row*(fifo_size-1))>>5); // + (3<<6);
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if (info->total_vram > 1*1024*1024) {
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switch (info->ram_type) {
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case WRAM:
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/* >1 MB WRAM */
|
||||
dsp_loop_latency += 9;
|
||||
n = 4;
|
||||
break;
|
||||
case SDRAM:
|
||||
case SGRAM:
|
||||
/* >1 MB SDRAM */
|
||||
dsp_loop_latency += 8;
|
||||
n = 2;
|
||||
break;
|
||||
default:
|
||||
/* >1 MB DRAM */
|
||||
dsp_loop_latency += 6;
|
||||
n = 3;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if (info->ram_type >= SDRAM) {
|
||||
/* <2 MB SDRAM */
|
||||
dsp_loop_latency += 9;
|
||||
n = 2;
|
||||
} else {
|
||||
/* <2 MB DRAM */
|
||||
dsp_loop_latency += 8;
|
||||
n = 3;
|
||||
}
|
||||
}
|
||||
|
||||
memcntl = aty_ld_le32(MEM_CNTL, info);
|
||||
t_rcd = ((memcntl >> 10) & 0x03) + 1;
|
||||
t_crd = ((memcntl >> 12) & 0x01);
|
||||
t_rp = ((memcntl >> 8) & 0x03) + 1;
|
||||
t_ras = ((memcntl >> 16) & 0x07) + 1;
|
||||
t_lat = (memcntl >> 4) & 0x03;
|
||||
|
||||
t_pfc = t_rp + t_rcd + t_crd;
|
||||
|
||||
t_rcc = max(t_rp + t_ras, t_pfc + n);
|
||||
|
||||
/* fifo_on<<6 */
|
||||
fifo_on = (2 * t_rcc + t_pfc + n - 1) << 6;
|
||||
|
||||
dsp_xclks_per_row = xclks_per_row>>dsp_precision;
|
||||
dsp_on = fifo_on>>dsp_precision;
|
||||
dsp_off = fifo_off>>dsp_precision;
|
||||
|
||||
pll->dsp_config = (dsp_xclks_per_row & 0x3fff) |
|
||||
((dsp_loop_latency & 0xf)<<16) |
|
||||
((dsp_precision & 7)<<20);
|
||||
pll->dsp_on_off = (dsp_off & 0x7ff) | ((dsp_on & 0x7ff)<<16);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
|
||||
struct pll_ct *pll)
|
||||
{
|
||||
#if DEBUG_PLL==1
|
||||
int pllmclk, pllsclk;
|
||||
#endif
|
||||
|
||||
u32 q, x; /* x is a workaround for sparc64-linux-gcc */
|
||||
x = x; /* x is a workaround for sparc64-linux-gcc */
|
||||
|
||||
pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per;
|
||||
|
||||
/* FIXME: use the VTB/GTB /3 post divider if it's better suited */
|
||||
|
||||
/* actually 8*q */
|
||||
q = info->ref_clk_per*pll->pll_ref_div*4/info->mclk_per;
|
||||
|
||||
if (q < 16*8 || q > 255*8)
|
||||
FAIL("mclk out of range\n");
|
||||
else if (q < 32*8)
|
||||
pll->mclk_post_div_real = 8;
|
||||
else if (q < 64*8)
|
||||
pll->mclk_post_div_real = 4;
|
||||
else if (q < 128*8)
|
||||
pll->mclk_post_div_real = 2;
|
||||
else
|
||||
pll->mclk_post_div_real = 1;
|
||||
pll->sclk_fb_div = q*pll->mclk_post_div_real/8;
|
||||
|
||||
#if DEBUG_PLL==1
|
||||
pllsclk = (1000000 * 2 * pll->sclk_fb_div) /
|
||||
(info->ref_clk_per * pll->pll_ref_div);
|
||||
|
||||
printk_debug("aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n",
|
||||
pllsclk, pllsclk / pll->mclk_post_div_real);
|
||||
#endif
|
||||
|
||||
pll->mclk_fb_mult = M64_HAS(MFB_TIMES_4) ? 4 : 2;
|
||||
|
||||
/* actually 8*q */
|
||||
q = info->ref_clk_per * pll->pll_ref_div * 8 /
|
||||
(pll->mclk_fb_mult * info->xclk_per);
|
||||
|
||||
if (q < 16*8 || q > 255*8)
|
||||
FAIL("mclk out of range\n");
|
||||
else if (q < 32*8)
|
||||
pll->xclk_post_div_real = 8;
|
||||
else if (q < 64*8)
|
||||
pll->xclk_post_div_real = 4;
|
||||
else if (q < 128*8)
|
||||
pll->xclk_post_div_real = 2;
|
||||
else
|
||||
pll->xclk_post_div_real = 1;
|
||||
pll->mclk_fb_div = q*pll->xclk_post_div_real/8;
|
||||
|
||||
#if DEBUG_PLL==1
|
||||
pllmclk = (1000000 * pll->mclk_fb_mult * pll->mclk_fb_div) /
|
||||
(info->ref_clk_per * pll->pll_ref_div);
|
||||
printk_debug("aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n",
|
||||
pllmclk, pllmclk / pll->xclk_post_div_real);
|
||||
#endif
|
||||
|
||||
/* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
|
||||
q = info->ref_clk_per*pll->pll_ref_div*4/vclk_per; /* actually 8*q */
|
||||
if (q < 16*8 || q > 255*8)
|
||||
FAIL("vclk out of range\n");
|
||||
else if (q < 32*8)
|
||||
pll->vclk_post_div_real = 8;
|
||||
else if (q < 64*8)
|
||||
pll->vclk_post_div_real = 4;
|
||||
else if (q < 128*8)
|
||||
pll->vclk_post_div_real = 2;
|
||||
else
|
||||
pll->vclk_post_div_real = 1;
|
||||
pll->vclk_fb_div = q*pll->vclk_post_div_real/8;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll)
|
||||
{
|
||||
u8 xpostdiv = 0;
|
||||
u8 mpostdiv = 0;
|
||||
u8 vpostdiv = 0;
|
||||
|
||||
if (M64_HAS(SDRAM_MAGIC_PLL) && (info->ram_type >= SDRAM))
|
||||
pll->pll_gen_cntl = 0x64; /* mclk = sclk */
|
||||
else
|
||||
pll->pll_gen_cntl = 0xe4; /* mclk = sclk */
|
||||
|
||||
switch (pll->mclk_post_div_real) {
|
||||
case 1:
|
||||
mpostdiv = 0;
|
||||
break;
|
||||
case 2:
|
||||
mpostdiv = 1;
|
||||
break;
|
||||
case 4:
|
||||
mpostdiv = 2;
|
||||
break;
|
||||
case 8:
|
||||
mpostdiv = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
pll->spll_cntl2 = mpostdiv << 4; /* sclk == pllsclk / mpostdiv */
|
||||
|
||||
switch (pll->xclk_post_div_real) {
|
||||
case 1:
|
||||
xpostdiv = 0;
|
||||
break;
|
||||
case 2:
|
||||
xpostdiv = 1;
|
||||
break;
|
||||
case 3:
|
||||
xpostdiv = 4;
|
||||
break;
|
||||
case 4:
|
||||
xpostdiv = 2;
|
||||
break;
|
||||
case 8:
|
||||
xpostdiv = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
if (M64_HAS(MAGIC_POSTDIV))
|
||||
pll->pll_ext_cntl = 0;
|
||||
else
|
||||
pll->pll_ext_cntl = xpostdiv; /* xclk == pllmclk / xpostdiv */
|
||||
|
||||
if (pll->mclk_fb_mult == 4)
|
||||
pll->pll_ext_cntl |= 0x08;
|
||||
|
||||
switch (pll->vclk_post_div_real) {
|
||||
case 2:
|
||||
vpostdiv = 1;
|
||||
break;
|
||||
case 3:
|
||||
pll->pll_ext_cntl |= 0x10;
|
||||
case 1:
|
||||
vpostdiv = 0;
|
||||
break;
|
||||
case 6:
|
||||
pll->pll_ext_cntl |= 0x10;
|
||||
case 4:
|
||||
vpostdiv = 2;
|
||||
break;
|
||||
case 12:
|
||||
pll->pll_ext_cntl |= 0x10;
|
||||
case 8:
|
||||
vpostdiv = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
|
||||
pll->vclk_post_div = vpostdiv;
|
||||
}
|
||||
|
||||
static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
|
||||
u8 bpp, union aty_pll *pll)
|
||||
{
|
||||
int err;
|
||||
if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
|
||||
return err;
|
||||
if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
|
||||
return err;
|
||||
aty_calc_pll_ct(info, &pll->ct);
|
||||
return 0;
|
||||
}
|
||||
#if 0
|
||||
static u32 aty_pll_ct_to_var(const struct fb_info_aty *info,
|
||||
const union aty_pll *pll)
|
||||
{
|
||||
u32 ref_clk_per = info->ref_clk_per;
|
||||
u8 pll_ref_div = pll->ct.pll_ref_div;
|
||||
u8 vclk_fb_div = pll->ct.vclk_fb_div;
|
||||
u8 vclk_post_div = pll->ct.vclk_post_div_real;
|
||||
|
||||
return ref_clk_per*pll_ref_div*vclk_post_div/vclk_fb_div/2;
|
||||
}
|
||||
|
||||
void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printk_debug("aty_set_pll_ct: about to program:\n"
|
||||
"refdiv=%d, extcntl=0x%02x, mfbdiv=%d\n"
|
||||
"spllcntl2=0x%02x, sfbdiv=%d, gencntl=0x%02x\n"
|
||||
"vclkcntl=0x%02x, vpostdiv=0x%02x, vfbdiv=%d\n"
|
||||
"clocksel=%d\n",
|
||||
pll->ct.pll_ref_div, pll->ct.pll_ext_cntl,
|
||||
pll->ct.mclk_fb_div, pll->ct.spll_cntl2,
|
||||
pll->ct.sclk_fb_div, pll->ct.pll_gen_cntl,
|
||||
pll->ct.pll_vclk_cntl, pll->ct.vclk_post_div,
|
||||
pll->ct.vclk_fb_div, aty_ld_le32(CLOCK_CNTL, info) & 0x03);
|
||||
#endif
|
||||
|
||||
aty_st_pll(PLL_REF_DIV, pll->ct.pll_ref_div, info);
|
||||
|
||||
aty_st_pll(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, info);
|
||||
aty_st_pll(MCLK_FB_DIV, pll->ct.mclk_fb_div, info); // for XCLK
|
||||
|
||||
aty_st_pll(SPLL_CNTL2, pll->ct.spll_cntl2, info);
|
||||
aty_st_pll(SCLK_FB_DIV, pll->ct.sclk_fb_div, info); // for MCLK
|
||||
|
||||
aty_st_pll(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, info);
|
||||
|
||||
aty_st_pll(EXT_VPLL_CNTL, 0, info);
|
||||
aty_st_pll(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, info);
|
||||
aty_st_pll(VCLK_POST_DIV, pll->ct.vclk_post_div, info);
|
||||
aty_st_pll(VCLK0_FB_DIV, pll->ct.vclk_fb_div, info);
|
||||
|
||||
if (M64_HAS(GTB_DSP)) {
|
||||
u8 dll_cntl;
|
||||
|
||||
if (M64_HAS(XL_DLL))
|
||||
dll_cntl = 0x80;
|
||||
else if (info->ram_type >= SDRAM)
|
||||
dll_cntl = 0xa6;
|
||||
else
|
||||
dll_cntl = 0xa0;
|
||||
aty_st_pll(DLL_CNTL, dll_cntl, info);
|
||||
aty_st_pll(VFC_CNTL, 0x1b, info);
|
||||
aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, info);
|
||||
aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, info);
|
||||
|
||||
mdelay(10);
|
||||
aty_st_pll(DLL_CNTL, dll_cntl, info);
|
||||
mdelay(10);
|
||||
aty_st_pll(DLL_CNTL, dll_cntl | 0x40, info);
|
||||
mdelay(10);
|
||||
aty_st_pll(DLL_CNTL, dll_cntl & ~0x40, info);
|
||||
}
|
||||
}
|
||||
static int dummy(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static struct aty_dac_ops aty_dac_ct = {
|
||||
set_dac: (void *)dummy,
|
||||
};
|
||||
|
||||
static struct aty_pll_ops aty_pll_ct = {
|
||||
var_to_pll: aty_var_to_pll_ct,
|
||||
#if 0
|
||||
pll_to_var: aty_pll_ct_to_var,
|
||||
set_pll: aty_set_pll_ct,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,484 @@
|
|||
/*
|
||||
* ATI Rage XL Initialization. Support for Xpert98 and Victoria
|
||||
* PCI cards.
|
||||
*
|
||||
* Copyright (C) 2002 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* stevel@mvista.com or source@mvista.com
|
||||
* Copyright (C) 2004 Tyan Computer.
|
||||
* Auther: Yinghai Lu yhlu@tyan.com
|
||||
* move to LinuxBIOS
|
||||
* This code is distributed without warranty under the GPL v2 (see COPYING) *
|
||||
*/
|
||||
#include <delay.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
#include "mach64.h"
|
||||
#include "atyfb.h"
|
||||
|
||||
#include "mach64_ct.c"
|
||||
|
||||
#define MPLL_GAIN 0xad
|
||||
#define VPLL_GAIN 0xd5
|
||||
|
||||
enum {
|
||||
VICTORIA = 0,
|
||||
XPERT98,
|
||||
NUM_XL_CARDS
|
||||
};
|
||||
|
||||
//static struct aty_pll_ops aty_pll_ct;
|
||||
|
||||
#define DEFAULT_CARD XPERT98
|
||||
static int xl_card = DEFAULT_CARD;
|
||||
|
||||
static const struct xl_card_cfg_t {
|
||||
int ref_crystal; // 10^4 Hz
|
||||
int mem_type;
|
||||
int mem_size;
|
||||
u32 mem_cntl;
|
||||
u32 ext_mem_cntl;
|
||||
u32 mem_addr_config;
|
||||
u32 bus_cntl;
|
||||
u32 dac_cntl;
|
||||
u32 hw_debug;
|
||||
u32 custom_macro_cntl;
|
||||
u8 dll2_cntl;
|
||||
u8 pll_yclk_cntl;
|
||||
} card_cfg[NUM_XL_CARDS] = {
|
||||
// VICTORIA
|
||||
{ 2700, SDRAM, 0x800000,
|
||||
0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
|
||||
0x82010102, 0x48803800, 0x005E0179,
|
||||
0x50, 0x25
|
||||
},
|
||||
// XPERT98
|
||||
{ 1432, WRAM, 0x800000,
|
||||
0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
|
||||
0x8000000A, 0x48833800, 0x007F0779,
|
||||
0x10, 0x19
|
||||
}
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
u8 lcd_reg;
|
||||
u32 val;
|
||||
} lcd_tbl_t;
|
||||
|
||||
static const lcd_tbl_t lcd_tbl[] = {
|
||||
{ 0x01, 0x000520C0 },
|
||||
{ 0x08, 0x02000408 },
|
||||
{ 0x03, 0x00000F00 },
|
||||
{ 0x00, 0x00000000 },
|
||||
{ 0x02, 0x00000000 },
|
||||
{ 0x04, 0x00000000 },
|
||||
{ 0x05, 0x00000000 },
|
||||
{ 0x06, 0x00000000 },
|
||||
{ 0x33, 0x00000000 },
|
||||
{ 0x34, 0x00000000 },
|
||||
{ 0x35, 0x00000000 },
|
||||
{ 0x36, 0x00000000 },
|
||||
{ 0x37, 0x00000000 }
|
||||
};
|
||||
|
||||
static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)
|
||||
{
|
||||
aty_st_8(LCD_INDEX, lcd_reg, info);
|
||||
return aty_ld_le32(LCD_DATA, info);
|
||||
}
|
||||
|
||||
static inline void aty_st_lcd(u8 lcd_reg, u32 val,
|
||||
struct fb_info_aty *info)
|
||||
{
|
||||
aty_st_8(LCD_INDEX, lcd_reg, info);
|
||||
aty_st_le32(LCD_DATA, val, info);
|
||||
}
|
||||
|
||||
static void reset_gui(struct fb_info_aty *info)
|
||||
{
|
||||
aty_st_8(GEN_TEST_CNTL+1, 0x01, info);
|
||||
aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
|
||||
aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
|
||||
mdelay(5);
|
||||
}
|
||||
|
||||
|
||||
static void reset_sdram(struct fb_info_aty *info)
|
||||
{
|
||||
u8 temp;
|
||||
|
||||
temp = aty_ld_8(EXT_MEM_CNTL, info);
|
||||
temp |= 0x02;
|
||||
aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b
|
||||
temp |= 0x08;
|
||||
aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 10b
|
||||
temp |= 0x0c;
|
||||
aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 11b
|
||||
mdelay(5);
|
||||
temp &= 0xf3;
|
||||
aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 00b
|
||||
temp &= 0xfd;
|
||||
aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST = 0b
|
||||
mdelay(5);
|
||||
}
|
||||
|
||||
static void init_dll(struct fb_info_aty *info)
|
||||
{
|
||||
// enable DLL
|
||||
aty_st_pll(PLL_GEN_CNTL,
|
||||
aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,
|
||||
info);
|
||||
|
||||
// reset DLL
|
||||
aty_st_pll(DLL_CNTL, 0x82, info);
|
||||
aty_st_pll(DLL_CNTL, 0xE2, info);
|
||||
mdelay(5);
|
||||
aty_st_pll(DLL_CNTL, 0x82, info);
|
||||
mdelay(6);
|
||||
}
|
||||
|
||||
static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,
|
||||
int hsync_enb)
|
||||
{
|
||||
reset_gui(info);
|
||||
aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
|
||||
aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);
|
||||
|
||||
mdelay(15);
|
||||
init_dll(info);
|
||||
aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
|
||||
mdelay(5);
|
||||
aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
|
||||
mdelay(6);
|
||||
reset_sdram(info);
|
||||
aty_st_8(CRTC_GEN_CNTL+3,
|
||||
hsync_enb ? 0x00 : 0x04, info);
|
||||
|
||||
aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);
|
||||
aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
|
||||
aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
|
||||
}
|
||||
|
||||
static int atyfb_xl_init(struct fb_info_aty *info)
|
||||
{
|
||||
int i, err;
|
||||
u32 temp;
|
||||
union aty_pll pll;
|
||||
const struct xl_card_cfg_t * card = &card_cfg[xl_card];
|
||||
|
||||
aty_st_8(CONFIG_STAT0, 0x85, info);
|
||||
mdelay(10);
|
||||
|
||||
/*
|
||||
* The following needs to be set before the call
|
||||
* to var_to_pll() below. They'll be re-set again
|
||||
* to the same values in aty_init().
|
||||
*/
|
||||
info->ref_clk_per = 100000000UL/card->ref_crystal;
|
||||
info->ram_type = card->mem_type;
|
||||
info->total_vram = card->mem_size;
|
||||
if (xl_card == VICTORIA) {
|
||||
// the MCLK, XCLK are 120MHz on victoria card
|
||||
info->mclk_per = 1000000/120;
|
||||
info->xclk_per = 1000000/120;
|
||||
info->features &= ~M64F_MFB_TIMES_4;
|
||||
}
|
||||
|
||||
/*
|
||||
* Calculate mclk and xclk dividers, etc. The passed
|
||||
* pixclock and bpp values don't matter yet, the vclk
|
||||
* isn't programmed until later.
|
||||
*/
|
||||
|
||||
if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;
|
||||
// if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
|
||||
|
||||
|
||||
aty_st_pll(LVDS_CNTL0, 0x00, info);
|
||||
aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);
|
||||
aty_st_pll(V2PLL_CNTL, 0x10, info);
|
||||
aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);
|
||||
aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);
|
||||
aty_st_pll(PLL_VCLK_CNTL, 0x00, info);
|
||||
aty_st_pll(VFC_CNTL, 0x1B, info);
|
||||
aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);
|
||||
aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
|
||||
aty_st_pll(SPLL_CNTL2, 0x03, info);
|
||||
aty_st_pll(PLL_GEN_CNTL, 0x44, info);
|
||||
|
||||
reset_clocks(info, &pll.ct, 0);
|
||||
mdelay(10);
|
||||
|
||||
aty_st_pll(VCLK_POST_DIV, 0x03, info);
|
||||
aty_st_pll(VCLK0_FB_DIV, 0xDA, info);
|
||||
aty_st_pll(VCLK_POST_DIV, 0x0F, info);
|
||||
aty_st_pll(VCLK1_FB_DIV, 0xF5, info);
|
||||
aty_st_pll(VCLK_POST_DIV, 0x3F, info);
|
||||
aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);
|
||||
aty_st_pll(VCLK2_FB_DIV, 0x00, info);
|
||||
aty_st_pll(VCLK_POST_DIV, 0xFF, info);
|
||||
aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);
|
||||
aty_st_pll(VCLK3_FB_DIV, 0x00, info);
|
||||
|
||||
aty_st_8(BUS_CNTL, 0x01, info);
|
||||
aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
|
||||
|
||||
aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
|
||||
aty_st_le16(CONFIG_STAT0, 0x0020, info);
|
||||
aty_st_le32(MEM_CNTL, 0x10151A33, info);
|
||||
aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
|
||||
aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
|
||||
aty_st_le32(DAC_CNTL, card->dac_cntl, info);
|
||||
aty_st_le16(GEN_TEST_CNTL, 0x0100, info);
|
||||
aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);
|
||||
aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);
|
||||
|
||||
aty_st_le32(HW_DEBUG, card->hw_debug, info);
|
||||
aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);
|
||||
aty_st_le16(GP_IO+2, 0x0000, info);
|
||||
aty_st_le16(GEN_TEST_CNTL, 0x0000, info);
|
||||
aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);
|
||||
aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);
|
||||
aty_st_le32(TIMER_CONFIG, 0x00000000, info);
|
||||
aty_st_le32(0xEC, 0x00000000, info);
|
||||
aty_st_le32(0xFC, 0x00000000, info);
|
||||
|
||||
for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
|
||||
aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
|
||||
}
|
||||
|
||||
aty_st_le16(CONFIG_STAT0, 0x00A4, info);
|
||||
mdelay(10);
|
||||
|
||||
aty_st_8(BUS_CNTL+1, 0xA0, info);
|
||||
mdelay(10);
|
||||
|
||||
reset_clocks(info, &pll.ct, 1);
|
||||
mdelay(10);
|
||||
|
||||
// something about power management
|
||||
aty_st_8(LCD_INDEX, 0x08, info);
|
||||
aty_st_8(LCD_DATA, 0x0A, info);
|
||||
aty_st_8(LCD_INDEX, 0x08, info);
|
||||
aty_st_8(LCD_DATA+3, 0x02, info);
|
||||
aty_st_8(LCD_INDEX, 0x08, info);
|
||||
aty_st_8(LCD_DATA, 0x0B, info);
|
||||
mdelay(2);
|
||||
|
||||
// enable display requests, enable CRTC
|
||||
aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
|
||||
// disable display
|
||||
aty_st_8(CRTC_GEN_CNTL, 0x40, info);
|
||||
// disable display requests, disable CRTC
|
||||
aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
|
||||
mdelay(10);
|
||||
|
||||
aty_st_pll(PLL_YCLK_CNTL, 0x25, info);
|
||||
|
||||
aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);
|
||||
aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);
|
||||
aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);
|
||||
aty_st_8(CUSTOM_MACRO_CNTL+1,
|
||||
(card->custom_macro_cntl>>8) & 0xff, info);
|
||||
|
||||
aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);
|
||||
aty_st_le32(MEM_CNTL, card->mem_cntl, info);
|
||||
aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
|
||||
|
||||
aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
|
||||
|
||||
aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
|
||||
mdelay(15);
|
||||
aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);
|
||||
mdelay(1);
|
||||
|
||||
reset_clocks(info, &pll.ct, 0);
|
||||
mdelay(50);
|
||||
reset_clocks(info, &pll.ct, 0);
|
||||
mdelay(50);
|
||||
|
||||
// enable extended register block
|
||||
aty_st_8(BUS_CNTL+3, 0x7B, info);
|
||||
mdelay(1);
|
||||
// disable extended register block
|
||||
aty_st_8(BUS_CNTL+3, 0x73, info);
|
||||
|
||||
aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
|
||||
|
||||
// disable display requests, disable CRTC
|
||||
aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
|
||||
// disable mapping registers in VGA aperture
|
||||
aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
|
||||
mdelay(50);
|
||||
// enable display requests, enable CRTC
|
||||
aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
|
||||
|
||||
// make GPIO's 14,15,16 all inputs
|
||||
aty_st_8(LCD_INDEX, 0x07, info);
|
||||
aty_st_8(LCD_DATA+3, 0x00, info);
|
||||
|
||||
// enable the display
|
||||
aty_st_8(CRTC_GEN_CNTL, 0x00, info);
|
||||
mdelay(17);
|
||||
// reset the memory controller
|
||||
aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
|
||||
mdelay(15);
|
||||
aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
|
||||
mdelay(30);
|
||||
|
||||
// enable extended register block
|
||||
aty_st_8(BUS_CNTL+3,
|
||||
(u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),
|
||||
info);
|
||||
// set FIFO size to 512 (PIO)
|
||||
aty_st_le32(GUI_CNTL,
|
||||
aty_ld_le32(GUI_CNTL, info) & ~0x3,
|
||||
info);
|
||||
|
||||
// enable CRT and disable lcd
|
||||
aty_st_8(LCD_INDEX, 0x01, info);
|
||||
temp = aty_ld_le32(LCD_DATA, info);
|
||||
temp = (temp | 0x01) & ~0x02;
|
||||
aty_st_le32(LCD_DATA, temp, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
|
||||
static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
|
||||
|
||||
static struct {
|
||||
u16 pci_id, chip_type;
|
||||
u8 rev_mask, rev_val;
|
||||
const char *name;
|
||||
int pll, mclk, xclk;
|
||||
u32 features;
|
||||
} aty_chips[] = {
|
||||
/* 3D RAGE XL PCI-66/BGA */
|
||||
{ 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
|
||||
/* 3D RAGE XL PCI-33/BGA */
|
||||
{ 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
|
||||
};
|
||||
#if 0
|
||||
static void aty_calc_mem_refresh(struct fb_info_aty *info,
|
||||
u16 id,
|
||||
int xclk)
|
||||
{
|
||||
int i, size;
|
||||
const int ragepro_tbl[] = {
|
||||
44, 50, 55, 66, 75, 80, 100
|
||||
};
|
||||
const int ragexl_tbl[] = {
|
||||
50, 66, 75, 83, 90, 95, 100, 105,
|
||||
110, 115, 120, 125, 133, 143, 166
|
||||
};
|
||||
const int *refresh_tbl;
|
||||
|
||||
if (IS_XL(id)) {
|
||||
refresh_tbl = ragexl_tbl;
|
||||
size = sizeof(ragexl_tbl)/sizeof(int);
|
||||
} else {
|
||||
refresh_tbl = ragepro_tbl;
|
||||
size = sizeof(ragepro_tbl)/sizeof(int);
|
||||
}
|
||||
|
||||
for (i=0; i < size; i++) {
|
||||
if (xclk < refresh_tbl[i])
|
||||
break;
|
||||
}
|
||||
|
||||
info->mem_refresh_rate = i;
|
||||
}
|
||||
#endif
|
||||
static void ati_ragexl_init(device_t dev) {
|
||||
u32 chip_id;
|
||||
u32 i;
|
||||
int j, k;
|
||||
u16 type;
|
||||
u8 rev;
|
||||
const char *chipname = NULL;
|
||||
int pll, mclk, xclk;
|
||||
|
||||
struct fb_info_aty *info;
|
||||
struct fb_info_aty info_t;
|
||||
struct resource *res;
|
||||
info = &info_t;
|
||||
|
||||
#define USE_AUX_REG 1
|
||||
|
||||
#if USE_AUX_REG==0
|
||||
res = &dev->resource[0];
|
||||
if(res->flags & IORESOURCE_IO) {
|
||||
res = &dev->resource[1];
|
||||
}
|
||||
info->ati_regbase = res->base+0x7ff000+0xc00;
|
||||
#else
|
||||
res = &dev->resource[2];
|
||||
if(res->flags & IORESOURCE_MEM) {
|
||||
info->ati_regbase = res->base+0x400; //using auxiliary register
|
||||
}
|
||||
|
||||
#endif
|
||||
printk_debug("ati_regbase = 0x%08x\r\n", info->ati_regbase);
|
||||
|
||||
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
|
||||
type = chip_id & CFG_CHIP_TYPE;
|
||||
rev = (chip_id & CFG_CHIP_REV)>>24;
|
||||
for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++)
|
||||
if (type == aty_chips[j].chip_type &&
|
||||
(rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
|
||||
chipname = aty_chips[j].name;
|
||||
pll = aty_chips[j].pll;
|
||||
mclk = aty_chips[j].mclk;
|
||||
xclk = aty_chips[j].xclk;
|
||||
info->features = aty_chips[j].features;
|
||||
goto found;
|
||||
}
|
||||
printk_debug("ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
|
||||
return ;
|
||||
|
||||
found:
|
||||
printk_debug("ati_ragexl_init: %s [0x%04x rev 0x%02x] ", chipname, type, rev);
|
||||
|
||||
if (M64_HAS(INTEGRATED)) {
|
||||
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
|
||||
if (mclk == 67 && info->ram_type < SDRAM)
|
||||
mclk = 63;
|
||||
}
|
||||
|
||||
// aty_calc_mem_refresh(info, type, xclk);
|
||||
info->pll_per = 1000000/pll;
|
||||
info->mclk_per = 1000000/mclk;
|
||||
info->xclk_per = 1000000/xclk;
|
||||
|
||||
// info->dac_ops = &aty_dac_ct;
|
||||
// info->pll_ops = &aty_pll_ct;
|
||||
info->bus_type = PCI;
|
||||
|
||||
|
||||
atyfb_xl_init(info);
|
||||
}
|
||||
|
||||
static struct device_operations ati_ragexl_graph_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ati_ragexl_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver ati_ragexl_graph_driver __pci_driver = {
|
||||
.ops = &ati_ragexl_graph_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_ATI_215XL,
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue