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soc/qualcomm/ipq40xx: Streamline memory map 

BUG=chrome-os-partner:49249
TEST=Able to compile and boot to depthcharge
BRANCH=none

Change-Id: I042fce58526b1c2add6b930429bf397e0dcfad2c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 66a630db6132e0e8a736b635d65e9e11c269b54a
Original-Change-Id: Ie2b6f59b3dbbac8117636c103d4d0acb782f4cb3
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333322
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14665
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Varadarajan Narayanan 2016-01-06 14:14:59 +05:30 committed by Patrick Georgi
parent 3a749ee654
commit 35d4a35669
1 changed files with 5 additions and 5 deletions
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10
src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
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@ -36,8 +36,8 @@ SECTIONS
PRERAM_CBFS_CACHE(0x0A0C0000, 93K)
TTB_SUBTABLES(0x0A0E0000, 4K)
TTB(0x0A0F0000, 16K)
TTB_SUBTABLES(0x0A0F4000, 4K)
REGION_END(wifi_imem_0, 0x0A100000)
/* ==^^^== WIFI_IMEM_0_END 0x0A100000 ==^^^== */
@ -57,8 +57,8 @@ SECTIONS
/* ==^^^== WIFI_IMEM_1_END 0x0A900000 ==^^^== */
DRAM_START(0x80000000)
RAMSTAGE(0x80640000, 128K)
SYMBOL(memlayout_cbmem_top, 0x89F80000)
POSTRAM_CBFS_CACHE(0x89F80000, 384K)
DMA_COHERENT(0x8A000000, 2M)
SYMBOL(memlayout_cbmem_top, 0x87280000)
POSTRAM_CBFS_CACHE(0x87280000, 384K)
RAMSTAGE(0x872e0000, 128K)
DMA_COHERENT(0x87300000, 2M)
}