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soc/intel/tigerlake: Correct FSP log interface 

select correct UART settings according to Kconfig
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

Add check for DEBUG_INTERFACE_TRACEHUB selection and set
"PcdDebugInterfaceFlags" UPD accordingly.

BUG=None
TEST=boot jslrvp board with Debug FSP and check FSP UART log
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
Ronak Kanabar 2020-03-04 19:03:47 +05:30 committed by Patrick Georgi
parent 840bef061f
commit 35d7843799
2 changed files with 17 additions and 1 deletions
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6
src/soc/intel/tigerlake/chip.h
View File

@ -193,6 +193,12 @@ struct soc_intel_tigerlake_config {
*/
uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* TraceHubMode config
* 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
*/
uint8_t TraceHubMode;
/* Debug interface selection */
enum {
DEBUG_INTERFACE_RAM = (1 << 0),

12
src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
View File

@ -69,8 +69,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Set CPU Ratio */
m_cfg->CpuRatio = 0;
/* Set debug interface flags */
m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO;
/* TraceHub configuration */
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
if (dev && dev->enabled && config->TraceHubMode) {
m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
m_cfg->PchTraceHubMode = config->TraceHubMode;
m_cfg->CpuTraceHubMode = config->TraceHubMode;
}
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);