From 35dc4b0ede0f4074351ac089d5abb1b5004cfa24 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 12 Feb 2021 16:04:27 -0700 Subject: [PATCH] soc/amd/cezanne: Enable uCode update TEST=Boot majolica and see microcode update CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8 microcode: patch id to apply = 0x0a50000b microcode: being updated to patch id = 0x0a50000b succeeded Signed-off-by: Raul E Rangel Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/cezanne/Kconfig | 5 ++++- src/soc/amd/cezanne/cpu.c | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 82ab3c40c3..9e5209f50e 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -40,11 +40,14 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART + select SOC_AMD_COMMON_BLOCK_UCODE select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + default 5568 + config CHIPSET_DEVICETREE string default "soc/amd/cezanne/chipset.cb" diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index b199d99251..2ec41a5196 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,8 @@ static void zen_2_3_init(struct device *dev) { setup_lapic(); set_cstate_io_addr(); + + amd_update_microcode_from_cbfs(); } static struct device_operations cpu_dev_ops = {