soc/intel/skylake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API. Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -173,6 +173,16 @@ uintptr_t soc_read_pmc_base(void)
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return (uintptr_t) (pmc_mmio_regs());
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}
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uint32_t *soc_pmc_etr_addr(void)
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{
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/*
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* The pointer returned must not be cached, because the address depends on the
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* MMCONF base address and the assigned PCI bus number, which both may change
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* during the boot process!
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*/
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return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR);
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}
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void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
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{
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DEVTREE_CONST struct soc_intel_skylake_config *config;
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