soc/intel/skylake: add soc implementation for ETR address API

Add soc implementation for the new ETR address API.

Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Michael Niewöhner 2019-11-02 12:14:06 +01:00 committed by Patrick Georgi
parent efe3cfb476
commit 35e76dde77
1 changed files with 10 additions and 0 deletions

View File

@ -173,6 +173,16 @@ uintptr_t soc_read_pmc_base(void)
return (uintptr_t) (pmc_mmio_regs());
}
uint32_t *soc_pmc_etr_addr(void)
{
/*
* The pointer returned must not be cached, because the address depends on the
* MMCONF base address and the assigned PCI bus number, which both may change
* during the boot process!
*/
return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR);
}
void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{
DEVTREE_CONST struct soc_intel_skylake_config *config;