mainboard/intel: Add MinnowBoard 3
This commit adds the initial scaffolding for the MinnowBoard 3 with Apollo Lake silicon. This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with name changes. Special adaptations for MinnowBoard 3 mainboard will follow in separate commits. Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Brenton Dong
Martin Roth
parent
b89b2c50c5
commit
35f03d9027
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@ -0,0 +1,17 @@
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if BOARD_INTEL_MINNOW3
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_INTEL_APOLLOLAKE
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_TABLES
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config MAINBOARD_DIR
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string
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default intel/minnow3
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config MAINBOARD_PART_NUMBER
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string
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default "Minnow3"
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endif # BOARD_INTEL_MINNOW3
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@ -0,0 +1,2 @@
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config BOARD_INTEL_MINNOW3
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bool "Minnow3"
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@ -0,0 +1,3 @@
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bootblock-y += bootblock.c
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ramstage-y += mainboard.c
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@ -0,0 +1,3 @@
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/*
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* Blank file required by build system assumptions of this file being present.
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*/
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@ -0,0 +1,6 @@
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Vendor name: Intel
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Board name: MinnowBoard 3
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <soc/lpc.h>
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void bootblock_mainboard_init(void)
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{
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lpc_configure_pads();
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}
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@ -0,0 +1,62 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/gpio.h>
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#if ENV_ROMSTAGE
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static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */
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PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */
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PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */
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PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */
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PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
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/* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */
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PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
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/* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */
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PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
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PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */
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PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */
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PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */
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PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */
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PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */
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PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */
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PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1),
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PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
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};
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#endif
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@ -0,0 +1,230 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
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# GPIO for PERST_0
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# If the Board has PERST_0 signal, assign the GPIO
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# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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register "prt0_gpio" = "GPIO_122"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0C16"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x28162828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x00181717"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10008"
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# Enable DPTF
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register "dptf_enable" = "1"
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# PL1 override 12000 mW: the energy calculation is wrong with the
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 12W.
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register "tdp_pl1_override_mw" = "12000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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register "hdaudio_pwr_gate_enable" = "1"
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register "hdaudio_bios_config_lockdown" = "1"
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# Enable lpss s0ix
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register "lpss_s0ix_enable" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route, i.e., if this route changes then the affected GPE
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# offset bits also need to be changed. This sets the PMC register
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# GPE_CFG fields.
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register "gpe0_dw1" = "PMC_GPE_N_31_0"
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register "gpe0_dw2" = "PMC_GPE_N_63_32"
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register "gpe0_dw3" = "PMC_GPE_SW_31_0"
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# Enable I2C0 for audio codec at 400kHz
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register "i2c[0]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 104,
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.fall_time_ns = 52,
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}"
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# Enable I2C2 bus early for TPM at 400kHz
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register "i2c[2]" = "{
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 57,
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.fall_time_ns = 28,
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}"
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# touchscreen at 400kHz
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register "i2c[3]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 76,
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.fall_time_ns = 164,
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}"
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# trackpad at 400kHz
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register "i2c[4]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 114,
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.fall_time_ns = 164,
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}"
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# digitizer at 400kHz
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register "i2c[5]" = "{
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 152,
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.fall_time_ns = 30,
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}"
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# Minimum SLP S3 assertion width 28ms.
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register "slp_s3_assertion_width_usecs" = "28000"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on # - Audio
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chip drivers/generic/max98357a
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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end
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device pci 11.0 off end # - ISH
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device pci 12.0 off end # - SATA
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device pci 13.0 off end # - Root Port 2 - PCIe-A 0
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device pci 13.1 off end # - Root Port 3 - PCIe-A 1
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device pci 13.2 off end # - Root Port 4 - PCIe-A 2
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device pci 13.3 off end # - Root Port 5 - PCIe-A 3
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device pci 14.0 on
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chip drivers/intel/wifi
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register "wake" = "GPE0_DW3_00"
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device pci 00.0 on end
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end
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end # - Root Port 0 - PCIe-B 0 - Wifi
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device pci 14.1 off end # - Root Port 1 - PCIe-B 1
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device pci 15.0 on end # - XHCI
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device pci 15.1 off end # - XDCI
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device pci 16.0 on # - I2C 0
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chip drivers/i2c/da7219
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register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
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register "btn_cfg" = "50"
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register "mic_det_thr" = "500"
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register "jack_ins_deb" = "20"
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register "jack_det_rate" = ""32ms_64ms""
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register "jack_rem_deb" = "1"
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register "a_d_btn_thr" = "0xa"
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register "d_b_btn_thr" = "0x16"
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register "b_c_btn_thr" = "0x21"
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register "c_mic_btn_thr" = "0x3e"
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register "btn_avg" = "4"
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register "adc_1bit_rpt" = "1"
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register "micbias_lvl" = "2600"
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register "mic_amp_in_sel" = ""diff""
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device i2c 1a on end
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end
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end
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
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device i2c 50 on end
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end
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end # - I2C 2
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device pci 16.3 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
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register "reset_delay_ms" = "20"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 10 on end
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end
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end # - I2C 3
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device pci 17.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
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register "wake" = "GPE0_DW1_15"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # - I2C 4
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device pci 17.1 on
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chip drivers/i2c/wacom
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register "generic" = "{
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.hid = WCOM50C1_HID,
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.cid = PNP0C50_CID,
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.desc = WCOM_DT_DESC,
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.irq = IRQ_LEVEL_LOW(GPIO_13_IRQ),
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}"
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register "hid_desc_reg_offset" = "0x1"
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device i2c 0x9 on end
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end
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end # - I2C 5
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device pci 17.2 off end # - I2C 6
|
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device pci 17.3 off end # - I2C 7
|
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 off end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 off end # - SPI 1
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device pci 19.2 off end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 off end # - SDIO
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device pci 1f.0 on # - LPC
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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||||
end
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device pci 1f.1 on end # - SMBUS
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end
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||||
end
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|
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@ -0,0 +1,42 @@
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x05, // DSDT revision: ACPI v5.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
/* global NVS and variables */
|
||||
#include <soc/intel/apollolake/acpi/globalnvs.asl>
|
||||
|
||||
/* CPU */
|
||||
#include <soc/intel/apollolake/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/apollolake/acpi/northbridge.asl>
|
||||
#include <soc/intel/apollolake/acpi/southbridge.asl>
|
||||
#include <soc/intel/apollolake/acpi/pch_hda.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <soc/intel/apollolake/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
/* Nothing Here Yet */
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
FLASH 16M {
|
||||
WP_RO@0x0 0x480000 {
|
||||
SI_DESC@0x0 0x1000
|
||||
IFWI@0x1000 0x27f000
|
||||
RO_VPD@0x280000 0x4000
|
||||
RO_SECTION@0x284000 0x1fc000 {
|
||||
FMAP@0x0 0x800
|
||||
COREBOOT(CBFS)@0x1000 0x1bb000
|
||||
RO_UNUSED@0x1bc000 0x40000
|
||||
}
|
||||
}
|
||||
MISC_RW@0x480000 0x30000 {
|
||||
UNIFIED_MRC_CACHE@0x0 0x21000 {
|
||||
RECOVERY_MRC_CACHE@0x0 0x10000
|
||||
RW_MRC_CACHE@0x10000 0x10000
|
||||
RW_VAR_MRC_CACHE@0x20000 0x1000
|
||||
}
|
||||
RW_ELOG@0x21000 0x3000
|
||||
RW_SHARED@0x24000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD@0x28000 0x2000
|
||||
RW_NVRAM@0x2a000 0x6000
|
||||
}
|
||||
RW_LEGACY(CBFS)@0xd30000 0x200000
|
||||
BIOS_UNUSABLE@0xf30000 0x4f000
|
||||
DEVICE_EXTENSION@0xf7f000 0x80000
|
||||
# Currently, it is required that the BIOS region be a multiple of 8KiB.
|
||||
# This is required so that the recovery mechanism can find SIGN_CSE
|
||||
# region aligned to 4K at the center of BIOS region. Since the
|
||||
# descriptor at the beginning uses 4K and BIOS starts at an offset of
|
||||
# 4K, a hole of 4K is created towards the end of the flash to compensate
|
||||
# for the size requirement of BIOS region.
|
||||
# FIT tool thus creates descriptor with following regions:
|
||||
# Descriptor --> 0 to 4K
|
||||
# BIOS --> 4K to 0xf7f000
|
||||
# Device ext --> 0xf7f000 to 0xfff000
|
||||
UNUSED_HOLE@0xfff000 0x1000
|
||||
}
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <fsp/api.h>
|
||||
#include <FspmUpd.h>
|
||||
#include "brd_gpio.h"
|
||||
|
||||
static const uint8_t Ch0_Bit_swizzling[] = {
|
||||
0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
|
||||
0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
|
||||
0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
|
||||
0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
|
||||
};
|
||||
static const uint8_t Ch1_Bit_swizzling[] = {
|
||||
0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
|
||||
0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
|
||||
0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
|
||||
0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
|
||||
};
|
||||
static const uint8_t Ch2_Bit_swizzling[] = {
|
||||
0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
|
||||
0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
|
||||
0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
|
||||
0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
|
||||
};
|
||||
static const uint8_t Ch3_Bit_swizzling[] = {
|
||||
0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
|
||||
0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
|
||||
0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
|
||||
0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
/* setup early gpio before memory */
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
|
||||
/* DRAM Config settings */
|
||||
memupd->FspmConfig.Package = 0x1;
|
||||
memupd->FspmConfig.Profile = 0xB;
|
||||
memupd->FspmConfig.MemoryDown = 0x1;
|
||||
memupd->FspmConfig.DDR3LPageSize = 0x0;
|
||||
memupd->FspmConfig.DDR3LASR = 0x0;
|
||||
memupd->FspmConfig.ScramblerSupport = 0x1;
|
||||
memupd->FspmConfig.ChannelHashMask = 0x36;
|
||||
memupd->FspmConfig.SliceHashMask = 0x9;
|
||||
memupd->FspmConfig.InterleavedMode = 0x2;
|
||||
memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
|
||||
memupd->FspmConfig.MinRefRate2xEnable = 0x0;
|
||||
memupd->FspmConfig.DualRankSupportEnable = 0x1;
|
||||
memupd->FspmConfig.RmtMode = 0x0;
|
||||
memupd->FspmConfig.MemorySizeLimit = 0x1800;
|
||||
memupd->FspmConfig.LowMemoryMaxValue = 0x0;
|
||||
memupd->FspmConfig.DisableFastBoot = 0x0;
|
||||
memupd->FspmConfig.HighMemoryMaxValue = 0x0;
|
||||
memupd->FspmConfig.DIMM0SPDAddress = 0x0;
|
||||
memupd->FspmConfig.DIMM1SPDAddress = 0x0;
|
||||
memupd->FspmConfig.Ch0_RankEnable = 0x3;
|
||||
memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
|
||||
memupd->FspmConfig.Ch0_DramDensity = 0x2;
|
||||
memupd->FspmConfig.Ch0_Option = 0x3;
|
||||
memupd->FspmConfig.Ch0_OdtConfig = 0x0;
|
||||
memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
|
||||
memupd->FspmConfig.Ch0_Mode2N = 0x0;
|
||||
memupd->FspmConfig.Ch0_OdtLevels = 0x0;
|
||||
memupd->FspmConfig.Ch1_RankEnable = 0x3;
|
||||
memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
|
||||
memupd->FspmConfig.Ch1_DramDensity = 0x2;
|
||||
memupd->FspmConfig.Ch1_Option = 0x3;
|
||||
memupd->FspmConfig.Ch1_OdtConfig = 0x0;
|
||||
memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
|
||||
memupd->FspmConfig.Ch1_Mode2N = 0x0;
|
||||
memupd->FspmConfig.Ch1_OdtLevels = 0x0;
|
||||
memupd->FspmConfig.Ch2_RankEnable = 0x3;
|
||||
memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
|
||||
memupd->FspmConfig.Ch2_DramDensity = 0x2;
|
||||
memupd->FspmConfig.Ch2_Option = 0x3;
|
||||
memupd->FspmConfig.Ch2_OdtConfig = 0x0;
|
||||
memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
|
||||
memupd->FspmConfig.Ch2_Mode2N = 0x0;
|
||||
memupd->FspmConfig.Ch2_OdtLevels = 0x0;
|
||||
memupd->FspmConfig.Ch3_RankEnable = 0x3;
|
||||
memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
|
||||
memupd->FspmConfig.Ch3_DramDensity = 0x2;
|
||||
memupd->FspmConfig.Ch3_Option = 0x3;
|
||||
memupd->FspmConfig.Ch3_OdtConfig = 0x0;
|
||||
memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
|
||||
memupd->FspmConfig.Ch3_Mode2N = 0x0;
|
||||
memupd->FspmConfig.Ch3_OdtLevels = 0x0;
|
||||
memupd->FspmConfig.RmtCheckRun = 0x0;
|
||||
memupd->FspmConfig.MrcDataSaving = 0x0;
|
||||
memupd->FspmConfig.MrcFastBoot = 0x0;
|
||||
|
||||
memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
|
||||
sizeof(Ch0_Bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
|
||||
sizeof(Ch1_Bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
|
||||
sizeof(Ch2_Bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
|
||||
sizeof(Ch3_Bit_swizzling));
|
||||
|
||||
memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
|
||||
memupd->FspmConfig.MsgLevelMask = 0x0;
|
||||
}
|
||||
Loading…
Reference in New Issue